We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOScompatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development. Introduction: Among non-volatile memory technologies, Spin-Transfer-Torque (STT) MRAM is seen as a credible candidate to replace SRAM in low level caches due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. This is reflected by major foundries and tool suppliers investing significant R&D resources into embedded MRAM past years. Recently they even started prototyping demonstrators, progressively reaching maturity for mass production [1-5]. However, STT-MRAM
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