limit, the power consumption and system efficiency caused by data movement between CPU and DRAM become performance bottlenecks. This "memory wall" accounts for up to half of the power consumption within a system. [4,5] The conventional 1T1C DRAM cell structure requires constant data refresh and write-back due to its volatile nature and destructive read operation, causing an enormous burden on power, bandwidth, and latency. [6,7] The volatile property originates from the offstate leakage current of the access silicon transistor, which becomes more severe as the technology node scales down, especially for advanced generations. [8,9] This off-state leakage can be reduced exponentially as the bandgap of the semiconductor increases, providing a unique advantage rather than enhanced electro-static control such as a gate-all-around structure. The use of wide bandgap semiconductors, specifically, amorphous oxide semiconductors (AOS) such as indium-gallium-zinc-oxide (IGZO) with a low thermal budget, has been recently proposed to replace the silicon channel in the DRAM cell due to its excellent leakage property with longer data retention. [10][11][12][13][14] The back-end-of-line compatibility with silicon technology can also significantly expand the bandwidth by increasing the interconnect density to logic units using 3D integration technology. The excellent leakage property leads to the relaxation of the storage capacitance requirement, which can revive the original design of a two-transistor cell (2T0C) using a much smaller gate capacitance from a second transistor to store charge. This structure not only brings in the unique advantage of a non-destructive read operation but also provides a viable solution for high-density 3D-DRAM without the stringent fabrication of high-aspect-ratio capacitors. [15][16][17] The data retention in such 2T0C DRAM cells based on AOS has been demonstrated to be up to 1000 s at capacitance values of a few fF and below. [18] However, it is imperative to note all the boosted retention time reported so far can only be achieved at negative hold voltages of the access or write transistor to suppress the leakage current to its minima. The leakage current increases exponentially with gate voltage in the subthreshold region, and will quickly drain out the charges in the storage node. [19] The data retention dependence on hold voltage has also been confirmed experimentally in AOS-based DRAM cells, showing an exponential decrease as the hold voltage increase Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO) exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobil...