Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for V<sub>t</sub> &gt; 0 V and I<sub>on</sub> &gt; 30 µA/µm

Rassoul, Nouredine; Belmonte, A.; Hody, Hubert; Dekkers, H.F.W.; Setten, Michiel J. van; Chasin, Ana Carolina da Matta; Sharifi, Shamin Houshmand; Sutar, Surajit; Magnarin, L.; Celano, Umberto; Puliyalil, Harinarayanan; Kundu, Shreya; Pak, M.; Teugels, Lieve; Tsvetanova, Diana; Bazzazian, N.; Vandersmissen, K.; Biasotto, C.; Batuk, Dmitry; Geypen, J.; Heijlen, J.; Delhougne, Romain; Kar, Gouri Sankar

doi:10.1109/vlsitechnologyandcir46769.2022.9830448

Cited by 15 publications

(10 citation statements)

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“…e) The compromise relationship between V th and I on for AOS transistors in non‐volatile DRAM applications. f) Benchmark of on‐current at V gs = V th + 1 V versus threshold voltage at 100 pA × W/L standard for single‐gate amorphous IGZO transistors at V ds = 1 V. [ 17,41–45 ]…”

Section: Resultsmentioning

confidence: 99%

“…Previous attempts of obtaining positive V th beyond 0.5 V have resulted in a significant drop of I on , as shown in the benchmark figure in Figure 2f. [17,[41][42][43][44][45] According to the percolation model, the carrier mobility of AOS decreases with reduced doping density, resulting in I on reduction as V th shifts positively. Using the synergistic energy band engineering in both channel and contacts, we successfully demonstrated a record-high I on of 14 µA µm −1 at a threshold voltage beyond 1.5 V for the first time, which is orders of magnitude higher than the previous works at similar V th .…”

Section: The Optimized Igzo Transistorsmentioning

confidence: 99%

“…As shown in the circuit schematic in Figure 3b, unlike in the traditional 1T1C structure, the write and read operations e) The compromise relationship between V th and I on for AOS transistors in non-volatile DRAM applications. f) Benchmark of on-current at V gs = V th + 1 V versus threshold voltage at 100 pA × W/L standard for single-gate amorphous IGZO transistors at V ds = 1 V. [17,[41][42][43][44][45] of the 2T0C DRAM cell are decoupled. This design of a high V th write transistor and a low V th read transistor is optimized for both high data retention and read margin under reasonable supply voltage.…”

Section: Multi-bit 2t0c Drammentioning

confidence: 99%

“…d) Energy band diagrams obtained from the contact area of IGZO transistors with direct nickel and inserted In-rich ITO.e) The compromise relationship between V th and I on for AOS transistors in non-volatile DRAM applications. f) Benchmark of on-current at V gs = V th + 1 V versus threshold voltage at 100 pA × W/L standard for single-gate amorphous IGZO transistors at V ds = 1 V [17,[41][42][43][44][45].…”

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confidence: 99%

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True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

et al. 2023

Advanced Materials

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limit, the power consumption and system efficiency caused by data movement between CPU and DRAM become performance bottlenecks. This "memory wall" accounts for up to half of the power consumption within a system. [4,5] The conventional 1T1C DRAM cell structure requires constant data refresh and write-back due to its volatile nature and destructive read operation, causing an enormous burden on power, bandwidth, and latency. [6,7] The volatile property originates from the offstate leakage current of the access silicon transistor, which becomes more severe as the technology node scales down, especially for advanced generations. [8,9] This off-state leakage can be reduced exponentially as the bandgap of the semiconductor increases, providing a unique advantage rather than enhanced electro-static control such as a gate-all-around structure. The use of wide bandgap semiconductors, specifically, amorphous oxide semiconductors (AOS) such as indium-gallium-zinc-oxide (IGZO) with a low thermal budget, has been recently proposed to replace the silicon channel in the DRAM cell due to its excellent leakage property with longer data retention. [10][11][12][13][14] The back-end-of-line compatibility with silicon technology can also significantly expand the bandwidth by increasing the interconnect density to logic units using 3D integration technology. The excellent leakage property leads to the relaxation of the storage capacitance requirement, which can revive the original design of a two-transistor cell (2T0C) using a much smaller gate capacitance from a second transistor to store charge. This structure not only brings in the unique advantage of a non-destructive read operation but also provides a viable solution for high-density 3D-DRAM without the stringent fabrication of high-aspect-ratio capacitors. [15][16][17] The data retention in such 2T0C DRAM cells based on AOS has been demonstrated to be up to 1000 s at capacitance values of a few fF and below. [18] However, it is imperative to note all the boosted retention time reported so far can only be achieved at negative hold voltages of the access or write transistor to suppress the leakage current to its minima. The leakage current increases exponentially with gate voltage in the subthreshold region, and will quickly drain out the charges in the storage node. [19] The data retention dependence on hold voltage has also been confirmed experimentally in AOS-based DRAM cells, showing an exponential decrease as the hold voltage increase Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO) exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobil...

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Section: Resultsmentioning

confidence: 99%

Section: The Optimized Igzo Transistorsmentioning

confidence: 99%

Section: Multi-bit 2t0c Drammentioning

confidence: 99%

mentioning

confidence: 99%

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True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

et al. 2023

Advanced Materials

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“…This is the reason why many semiconductor industry and research groups have studied the a‐IGZO channel material for stackable static random access memory (SRAM) and 3D dynamic random access memory (DRAM) Cell transistor. [ 41,42 ] An optical microscopy (OM) image of the integrated device is shown in Figure 3h. The a‐IGZO transistor was fabricated with a W/L ratio of 100 µm/10 µm, and the mReLU was patterned at 50 µm × 50 µm on the drain region of the a‐IGZO transistor (Figure S4, Supporting Information).…”

Section: Resultsmentioning

confidence: 99%

Preventing Vanishing Gradient Problem of Hardware Neuromorphic System by Implementing Imidazole‐Based Memristive ReLU Activation Neuron

Kim

Lee

et al. 2023

Advanced Materials

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With advances in artificial intelligent services, brain‐inspired neuromorphic systems with synaptic devices are recently attracting significant interest to circumvent the von Neumann bottleneck. However, the increasing trend of deep neural network parameters causes huge power consumption and large area overhead of a nonlinear neuron electronic circuit, and it incurs a vanishing gradient problem. Here, a memristor‐based compact and energy‐efficient neuron device is presented to implement a rectifying linear unit (ReLU) activation function. To emulate the volatile and gradual switching of the ReLU function, a copolymer memristor with a hybrid structure is proposed using a copolymer/inorganic bilayer. The functional copolymer film developed by introducing imidazole functional groups enables the formation of nanocluster‐type pseudo‐conductive filaments by boosting the nucleation of Cu nanoclusters, causing gradual switching. The ReLU neuron device is successfully demonstrated by integrating the memristor with amorphous InGaZnO thin‐film transistors, and achieves 0.5 pJ of energy consumption based on sub‐10 µA operation current and high‐speed switching of 650 ns. Furthermore, device‐to‐system‐level simulation using neuron devices on the MNIST dataset demonstrates that the vanishing gradient problem is effectively resolved by five‐layer deep neural networks. The proposed neuron device will enable the implementation of high‐density and energy‐efficient hardware neuromorphic systems.

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Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

Ryu,

Kang,

Cho

et al. 2024

Adv Materials Technologies

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Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

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Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for V_t > 0 V and I_on > 30 µA/µm

Cited by 15 publications

References 1 publication

True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

Preventing Vanishing Gradient Problem of Hardware Neuromorphic System by Implementing Imidazole‐Based Memristive ReLU Activation Neuron

Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

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Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm

Cited by 15 publications

References 1 publication

True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

Preventing Vanishing Gradient Problem of Hardware Neuromorphic System by Implementing Imidazole‐Based Memristive ReLU Activation Neuron

Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

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Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for V_t > 0 V and I_on > 30 µA/µm