True Nonvolatile High‐Speed DRAM Cells Using Tailored Ultrathin IGZO

Abstract

limit, the power consumption and system efficiency caused by data movement between CPU and DRAM become performance bottlenecks. This "memory wall" accounts for up to half of the power consumption within a system. [4,5] The conventional 1T1C DRAM cell structure requires constant data refresh and write-back due to its volatile nature and destructive read operation, causing an enormous burden on power, bandwidth, and latency. [6,7] The volatile property originates from the offstate leakage current of the access silicon transistor, which becomes more severe as the technology node scales down, especially for advanced generations. [8,9] This off-state leakage can be reduced exponentially as the bandgap of the semiconductor increases, providing a unique advantage rather than enhanced electro-static control such as a gate-all-around structure. The use of wide bandgap semiconductors, specifically, amorphous oxide semiconductors (AOS) such as indium-gallium-zinc-oxide (IGZO) with a low thermal budget, has been recently proposed to replace the silicon channel in the DRAM cell due to its excellent leakage property with longer data retention. [10][11][12][13][14] The back-end-of-line compatibility with silicon technology can also significantly expand the bandwidth by increasing the interconnect density to logic units using 3D integration technology. The excellent leakage property leads to the relaxation of the storage capacitance requirement, which can revive the original design of a two-transistor cell (2T0C) using a much smaller gate capacitance from a second transistor to store charge. This structure not only brings in the unique advantage of a non-destructive read operation but also provides a viable solution for high-density 3D-DRAM without the stringent fabrication of high-aspect-ratio capacitors. [15][16][17] The data retention in such 2T0C DRAM cells based on AOS has been demonstrated to be up to 1000 s at capacitance values of a few fF and below. [18] However, it is imperative to note all the boosted retention time reported so far can only be achieved at negative hold voltages of the access or write transistor to suppress the leakage current to its minima. The leakage current increases exponentially with gate voltage in the subthreshold region, and will quickly drain out the charges in the storage node. [19] The data retention dependence on hold voltage has also been confirmed experimentally in AOS-based DRAM cells, showing an exponential decrease as the hold voltage increase Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO) exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobil...

2D Vertical and Horizontal Memristors Based on Large-Area 2D Tellurium Film

“…In recent years, research of low-dimensional materials in fields such as light, electricity, and magnetism has received continued attention. − The increasing amount of data requires high-density, high-speed, and high-stability memristors for calculation and simulation, − as traditional dynamic random-access memory (DRAM) and flash memory cannot meet these requirements well. − Therefore, it is urgent to develop a high-performance memristor. Te compound-based memory has developed since the past century, most of them are based on phase transitions of binary or ternary compounds such as GeTe, GeSbTe, GeSeTe, etc., − while few reports focus on pure Te-based memory.…”

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway

“…Amorphous oxide semiconductors (AOSs) with extremely low off-currents originating from their electronic structure − have attracted considerable interest for applications in the storage chip industry, enabling the development of capacitorless dynamic random-access memory (DRAM) architecture and high-density DRAM technologies. − In contrast to thin-film transistors (TFTs) for flat panel displays, storage chips employ vertically stacked complex device architectures to achieve higher device density, − posing challenges in electrode processing, and increasing the importance of contact issues between AOSs and electrodes. − Process-derived poor contacts and a substantial Schottky barrier resulting from the intrinsic energy level mismatch between the work function of the electrode metal and the electron affinity of AOSs eventually lead to excessively high contact resistance ( R C ), thereby degrading field-effect mobility and power consumption. Recently, many works have proposed methods to solve high contact resistance between AOSs and metal electrodes, which may be categorized into several main strategies: additional deposition of a highly conductive oxide interlayer, − oxidation of the metal contact surface resulting in the formation of high concentration oxygen vacancies on the AOS contact surface via high-temperature annealing, − penetration of metal ions into the AOS layer, , and surface treatment with plasma. − These methods, which involve high-energy or multistep processes, offer effective solutions for the high contact resistance of the exposed upper surface of oxide semiconductors, as shown in Figure a, but are almost impossible to apply to buried contact or deep vertical interfaces within nanoscale complex structures.…”

“…Amorphous oxide semiconductors (AOSs) with extremely low off-currents originating from their electronic structure 1 − 4 have attracted considerable interest for applications in the storage chip industry, enabling the development of capacitorless dynamic random-access memory (DRAM) architecture and high-density DRAM technologies. 5 − 8 In contrast to thin-film transistors (TFTs) for flat panel displays, storage chips employ vertically stacked complex device architectures to achieve higher device density, 9 − 11 posing challenges in electrode processing, and increasing the importance of contact issues between AOSs and electrodes. 12 − 14 Process-derived poor contacts and a substantial Schottky barrier resulting from the intrinsic energy level mismatch between the work function of the electrode metal and the electron affinity of AOSs eventually lead to excessively high contact resistance ( R C ), thereby degrading field-effect mobility and power consumption.…”

Optimizing the Performance of the Atomic-Layer-Deposited Zinc–Tin-Oxide Thin Film Transistor by Ozone Treatment and Thermal Annealing

“…Incorporating hydrogen atoms during the thin film growth and post-deposition processes and their interaction with the oxygen ions or defects must also be considered. − The structural distortions and internal stresses imposed by the thin film deposition and device fabrication processes also affect the device’s performance. Long-term stability under negative or positive gate bias stress (NBS or PBS) is a crucial device performance metric, which is also influenced by these factors. − In this regard, post-fabrication thermal annealing can be a feasible method to mitigate the issues related to oxygen defects and structural distortions. − …”