Esta es la versión de autor de la comunicación de congreso publicada en: This is an author produced version of a paper published in: IEEE Workshop on Signal Processing Systems, SIPS 1998, IEEE, 1998 Abstract -In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. Main results show that the canonical form presents the less occupation and the higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.
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