A study about FPGA-based digital filters

Valls, Javier; Peiro, M.M.; Sansaloni, T.; Boemo, Eduardo

doi:10.1109/sips.1998.715782

Cited by 15 publications

(6 citation statements)

References 11 publications

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“…To show the advantage of the PDR image filter comparing to the standard static image filter for Gauss noise (standard average filter, SA filter [16]) and Salt & Pepper noise(standard median filter, SM filter [17]), we compare the PSNR of the output image from them. As showed in TABLE I, the proposed PDR filter gains better PSNR by 4~5db.…”

Section: ) Psnr Of the Pdr Filtermentioning

confidence: 99%

Image filtering using partially and dynamically reconfiguration

Yang

Zhang

Lai

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically.Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks as required in PDR system. And we demo the system with an image filter aimed at filtering out mix-noise. The experiment results show that the proposed PDR system meets the requirement of the run-time image filter by its flexibility, fast reconfiguration speed, and saving of logic resource.

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Section: ) Psnr Of the Pdr Filtermentioning

confidence: 99%

Image filtering using partially and dynamically reconfiguration

Yang

Zhang

Lai

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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“…To reduce the switching activities high speed bypass multiplier is described in [12].to enhance the fast carry generation carry look ahead function is employed in the addition part. Digit serial FIR for both symmetrical and anti symmetrical cases is described in [14].By switching to FIR filtering is realized using the online processing is described in [15].…”

Section: Introductionmentioning

confidence: 99%

Systolic Fir Filter using Bypass Multiplier

Swarnalatha,

Hariveena,

Vuppala

2019

IJEAT

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In DSP the most common function is Finite Impulse Response (FIR) filter which is realized in field Programmable gate Arrays (FPGAs). For efficient Very Large Scale Integration (VLSI) computation systolic FIR filter architecture has attractive models. High speed is the major concern for fast computation in real time Digital Signal Processing (DSP) applications. In conventional systolic FIR filter method uses general array multiplier structure which takes more time to compute the process with high design complexity with less power. To overcome this problem the systolic FIR filter utilizing Bypass Feed Direct Multiplier(BFDM) is proposed. The proposed method 16 tap systolic FIR parallel processing offers less delay with less design complexity which is used in image and signal processing applications. The proposed method is simulated using Xilinx ISE 12.4 ISE tool and the functions are evaluated by MODELSIM 6.3C.

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“…FIR filters in FPGA is not a new concept. There are many published papers regarding this subject [2]- [4]. However, the length of the filters or the number of taps is relatively small compared to the scale of this application, even for newer published works [5], [6].…”

Section: Introductionmentioning

confidence: 99%

FIR filter implementation for high-performance application in a high-end FPGA

Pijetlović¹,

Subotic²,

Marinkovic³

et al. 2019

Telfor J

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In this paper a high-performance application which uses multiple 48k tap FIR filters is presented. Due to its size, complexity and restrictions such as real-time, small latency and large memory bandwidth, the filter was implemented in UltraScale+, a high-end FPGA from Xilinx. The system was verified using a gold reference model written in C (high-level algorithm verification) and an analytical model calculated manually. The system was also tested using a development board and SystemVerilog (for register-transfer level and timing verification). The obtained results show a perfect match between the reference models and the actual output. The main novelty of the paper is the implementation of such an immense real-time signal processing system based on FIR filters consisting of over a million taps all together in a single design spread out across a chip containing three dies. Details about the resources allocated within the FPGA are also given in a table in the results chapter.

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A study about FPGA-based digital filters

Cited by 15 publications

References 11 publications

Image filtering using partially and dynamically reconfiguration

Image filtering using partially and dynamically reconfiguration

Systolic Fir Filter using Bypass Multiplier

FIR filter implementation for high-performance application in a high-end FPGA

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