Image filtering using partially and dynamically reconfiguration

Yang, HuaQiu; Zhang, Fanjiong; Lai, Jinmei; Wang, Yan

doi:10.1109/icsict.2010.5667280

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…Configuring an architecture on-the-go such as dynamic configuration, allows a system to be dynamically modified during its normal operation without the need for resetting the remaining circuitry or removing any reconfigurable blocks for programming. The reconfiguration also optimizes the necessary component count and power consumption, making it suitable for data path components in media signal processing, networking, and cryptography [4]- [18].…”

Section: Introductionmentioning

confidence: 99%

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Allwin¹,

Chen²

2021

JCC

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Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm 2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

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Section: Introductionmentioning

confidence: 99%

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Allwin¹,

Chen²

2021

JCC

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Research on reconfiguration technology based on SOPC for PXI instrument

Zhao

Hou

Wang

2015

2015 Ieee Autotestcon

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The traditional PXI instrument generally has fixed function and its firmware is difficult to upgrade. To overcome this problem, the reconfigurable PXI instrument is proposed to meet different requirements. The design is implemented by using Field Programmable Gate Arrays (FPGAs) with reconfigurable function. In this paper, in order to satisfy the different vehicle bus test requirements, a reconfigurable serial communication module is designed, and the serial communication interface and protocol of this module can be reconfigured dynamically. The design is based on Dynamic Partial Reconfiguration (DPR) which is implemented by the Xilinx Virtex-5 FPGA supporting the System on Programmable Chip (SOPC). As a character, online reconfiguration of local and remote is supported. The test results indicate that 5 different protocols are supported. In the meantime, the design is also with the character of real-time. When the configuration data is 167310 Bytes, the time of local reconfiguration is less than 5ms and the remote reconfiguration is accomplished within 70ms.

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Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing

Llamocca

Pattichis

2014

ACM Trans. Reconfigurable Technol. Syst.

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There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of dynamically reconfigurable systems to new domains, such as digital video processing. We develop a dynamically reconfigurable 2D FIR filtering system that can meet real-time constraints in energy, performance, and accuracy (EPA). The real-time constraints are automatically generated based on user input, image types associated with video communications, and video content. We first generate a set of Pareto-optimal realizations, described by their EPA values and associated 2D FIR hardware description bitstreams. Dynamic management is then achieved by selecting Pareto-optimal realizations that meet the automatically generated time-varying EPA constraints. We validate our approach using three different 2D Gaussian filters. Filter realizations are evaluated in terms of the required energy per frame, accuracy of the resulting image, and performance in frames per second. We demonstrate dynamic EPA management by applying a Difference of Gaussians (DOG) filter to standard video sequences. For video frame sizes that are equal to or larger than the VGA resolution, compared to a static implementation, our dynamic system provides significant reduction in the total energy consumption (>30%).

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Image filtering using partially and dynamically reconfiguration

Cited by 3 publications

References 13 publications

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Research on reconfiguration technology based on SOPC for PXI instrument

Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing

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