Lifting folded pipelined discrete wavelet packet transform architecture

VLSI Architectures for Lifting-Based Discrete Wavelet Packet Transform

“…Circuit simulation and but also leads to significant power dissipation because of the implementation results demonstrate that the proposed folded intensive memory R/W (read and write) operations. The architecture computes the multilevel DWPT much faster than RPA-based (recursive pyramid algorithm) folded architecture the conventional single-PE architecture, while the hardware cost [11] was proposed compute multilevel DWPT In this paper, we propose an efficient folded architecture for computing multilevel DWPT, which is derived from the implementation of the lifting-based wavelet filter (PE), only DDC architecture. In this folded DDC architecture, the one wavelet filter (folded PE) is folded to compute the hardware complexity is further reduced to one PE, through multiple groups of butterflies simultaneously at each level.…”

Very large scale integration architectures of discrete transforms for digital signal processing applications

“…The folded DWPT architecture is actually a modified recursive DWPT architecture, However, the actual circuit simulation and implementation results are not reported in [95]. The Paya's method has high scheduling and control complexity, which also introduces large numbers of switches, multiplexers and control signals.…”

“…The generalized 1level folded DDC architecture is depicted by Figure 5.18 (b). To configure the DDC for the jth DWPT decomposition, the I-to-1 switches SWA and SWB select the data samples from the input port j of the switches, which are delayed by 2/+1 cycles (j = 0, 1, ... ,1 -2) for reordering, or not delayed at all (j =1-1) for output, as illustrated by As described previously, the Paya's folded architecture [95] maps a 3-level 5/3 registers in the configurable PE is shown in Figure 5.18 (a). In order to appropriately wavelet filter with many extra switches and registers.…”

“…filter implementations, including the proposed three DWPT architectures and the Because Paya only presents the folded architecture for the 5/3 filter in[95], a Paya's architecture, are provided in Table5 10…”

“…In terms of storage units, the Trenas's pipeline architecture has the largest memory requirements. Both Trenas' and Aroutchelvame's recursive architectures have a memory capacity of size N. In contrast to other DWPT architectures, the Paya's folded architecture[95] and our DDC architecture use switches and registers to feedback or buffer the intermediate data during the DWPT computation. Compared with the memory-based architectures, these two architectures may be more areaefficient because switches and shift registers generally consume lesser silicon area than memory.…”