Enormous efforts have been made towards the next generation of flexible, low-cost, environmentally benign printed electronics. In this regard, advanced materials for the printed conductive lines and interconnects are of significant importance. To improve efficiency and effectiveness, for several decades, conductive fillers have been filled into dispersants, which lead to the so-called electrically conductive composites (ECCs), which are a key material to the printed electronics varying from substituting the traditional solders to finding new applications in the blooming field of flexible printed electronics. ECCs in various formulations have converged in the current efforts to develop platforms with the desired specifications of electrical and thermal conductance, mechanical strength, and others. This platform is highly versatile and valuable for the emerging novel electronic devices, which emphasize tailoring processing conditions to cater to the key functional materials to optimize outcomes. The properties obtained can facilitate decisions about modifications to treatment. Noble metal fillers, such as silver flakes, have long been studied as active fillers for the ECCs. Owing to the recent progress in nanotechnology and surface modifications, many new avenues have opened for them. By taking advantage of the well-developed surface chemistry of these materials, researchers are enhancing their electrical conductivity, which is essential for broader applications. In recent years, the advances of ECCs have benefited the development of the applications of optoelectronics, e-papers, electromagnetic

A system-on-chip passive UHF RFID tag with embedded temperature sensor is developed in a standard 0.18µm CMOS process for the EPC Gen-2 protocol from 860-960MHz [1]. Flip-chip technology is used to bond the developed tag IC to an antenna to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. Figure 17.1.1 shows the block diagram of the tag IC. Multiple supply voltages, generated by a power management unit (PMU) using a separate-storage-capacitor technique to save area, are employed to optimize the performance of individual building blocks, while minimizing the total power consumption. A dualpath clock generator is used to generate on-chip clocks for signal processing to support both applications with either very accurate link frequency or very low power consumption. A low-power temperature sensor is also embedded with a gain-compensation technique that makes use of current correlation from the same bandgap reference (BGR) for the clock generator to reduce the temperature sensing error due to process variations.Figure 17.1.2 shows the PMU. The rectifier (RECT1) supplies the 670nA BGR while the core RF-DC conversion is performed by a triple-output rectifier (RECT2). Further supply regulation is done using low-dropout regulators (LDRs). For the duration of PW (=Tari/2) [1], as the RF input is significantly attenuated due to the data modulation, the rectifier becomes inactive, and a storage capacitor C S is employed to supply both the load current I L and the reverse leakage current I leak that flows back to the rectifier, which results in a ripple voltage of VR CS =(I L +I leak )×PW/C S . In existing work [2], all the blocks share one single capacitor C S , which needs to be large enough to meet the ripple voltage requirement of the most noise-sensitive block. To provide a highly stable current for the dual-path clock generator, the BGR is required to have a small supply ripple of 0.1V, and, as a result, the single C S would need to be at least 1.75nF to supply the nominal total I L of 14µA when Tari=25µs. In our work, three separate capacitors, C Sx (x=1,2,3), are employed for different blocks with different optimal ripple voltages (0.4V, 0.25V, 0.1V, respectively), which helps to significantly reduce the total capacitance to 805pF, even with >10% margins. The switches S x (x=1,2,3) are controlled by the demodulator's output to cut off I leak during PW, which helps further reduce both the sizes of C Sx and the required input power for replenishing. M ST1 and M ST2 are used for start-up. High voltages of 3.5V and 7.8V, used for programming the OTP memory, are generated by three charge pumps (QPs). During the WRITE operation, a VCO is activated to regulate the QP_VPP's output at 7.8V with an output current up to 20µA. With sufficient input power, the power detector (PD) sends a Power-Good (PG) signal to turn on S 4 to power up LDR 3 for the injection-locked frequency divider (ILFD) in the dual-path clock generator. Figure 17...

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