IT IS WELL KNOWN that the current technological improvements of HMOs', DMOS' and VMOS3 will tend t o shift the emphasis of technology t o very high performance of switching speed, high frequency operation, low power dissipation and fine patterning.To obtain higher performance MOS integrated circuits associated with a short channel, high speed and high packing density, a submicron channel MOS (SMOS) IC technology approach will be reported. Some basic processing, parameters and performances, such as gate threshold voltage, punchthrough breakdown voltage, submicron channel length, double ion implantation and scale down configuration, will be described and discussed. The IC circuit design configuration of an Enhancement/Depletion (E/D) inverter circuit and the propagation delay time and power dissipation with a Zl-stage ring oscillator will also be presented. Figure 1 shows the key points of the processing of the SMOS device. By utilizing some modification of conventional local oxidation teehnology, continuous change of oxide film thickness in the Bird's Beak shape can be realized, as shown in Figure l(a). After removing the nitride film, boron ions will be deeply implanted into the silicon substrate with the high energy of 400keV. The penetration depth of boron ion implantation into the P-type substrate varies inversely with the oxide thickness change, as shown in A, B and C in Figure l(b). After this boron ion implantation, arsenic ions are implanted at 200keV through the same oxide film, Figure l(c). This double ion implantation of boron and arsenic provides the self-alignment between the source and submicron channel regions.After etching all oxide films as shown in Figure l(d), a conventional silicon gate MOS-IC process technology can be utilized; for example, gate oxidation, self-aligned polysilicon gate, arsenic diffusion for source and drain regions, and aluminum interconnection. As a result, a submicron channel MOS device structure can be fabricated, as shown in Figure 2(a). Figure 2(b) shows a SEM photograph of SMOS device cross section.A feature is the P-type region under the polysilicon gate electrode, created by deep boron ion implantation. This P-type region can be controlled precisely in submicron lengths by choosing an appropriate boron ion implantation energy and dose density. An example of boron impurity profile along -the silicon __ surface in this P-type region is shown in Figure 3. The Ndrift layer also plays an important role in preventing the failure of punchthrough breakdown voltage and in increasing the conduetance of SMOS.According to a theoretical analysis of impurity distribution around the submicron channel region, the channel length of SMOS can be controlled from 0.16pm to 0.90pm by using specific process conditions.In typical experimental devices, the actual channel length and the junction depth of source and drain were 0.8pm and 0.4pm, respectively. The threshold voltage was controlled in the range of 0.6V t o 4.2V by choosing a channel boron ion dose from 2x101'em-' to 8x101'cm-'. The ...
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