A planarized device isolution process (PLANTI) has been developed and optimized by using a deep-trench isolation technology combined with a local oxidation of silicon (LOCOS) process for self-aligned double polysilicon bipolar integrated circuit fabrication. To obtain a desirable trench etch profile and a uniform polysilicon etchback process, reactive ion etch processes have been optimized in terms of gas ratio, pressure, and power density. As a result of deep-trench isolation, the coUector-to-substrate capacitance was minimized at 9.0 fF for a bipolar transistor with a total area of 7 x 11 ~m 2, while maintaining a transistor-to-transistor isolation voltage at 25V. A bipolar cut-off frequency of 15.5 GHz and an ECLgate delay time of 66 ps were achieved. As proof-of-technology, four digital]analog circuits have been successfully fabricated. An amplifier with a bandwidth of 2.6 GHz and a gain of 20 dB, a frequency divider and a 8-bit shift register with clock frequencies of 5.2 GHz and 2 GHz, respectively, and a dual 4-bit analog-to-digital (A/D) converter with a sampling rate of 2.0 Gs/s were successfully demonstrated. A yield of 85% was achieved for the converter circuit. Furthermore, the PLANTI process was also successfully applied to an advanced BiCMOS process.As device geometries have continued to shrink and circuit complexity has continued to grow, device isolation has become a major factor limiting circuit density. Conventional LOCOS isolation is a well-established technology, having been used in production for many years. However, this isolation scheme alone is not particularly well suited for use on very high density circuits. A well-known disadvantage of this process is lateral bird's-beak encroachment, which limits device geometry and therefore circuit density.Trench isolation technology has been developed and applied to both bipolar (1-2) and MOS (3-5) technologies. It has the advantage of being nonencroaching, with trench widths on the order of 1.2 ~m, making it suitable for high density circuits. Nevertheless, how to integrate deeptrench as a part of complete device isolation and how to maintain a planar surface are remaining issues (4), in addition to some electrical concerns. Consequences of a nonplanar surface includes photolithographic issues as well as complications and difficulties encountered during subsequent device fabrication.This paper presents an optimized device isolation (PLANTI) process that combines deep-trench and LOCOS. Using the PLANTI process, a planar surface on top of deep-trench is achieved, which is ideal for VLSI applications. To achieve the PLANTI process, deep-trench profile and trench surface planarity and uniformity are the most important factors. In this paper, optimization of deep-trench silicon RIE and polysilicon etchback processes are addressed. The PLANTI process has been applied to fabrication of double polysilicon bipolar transistors, MOSFETs, digital and analog circuits. Bipolar transistors with a cut-off frequency of 15.5 GHZ and a high performance 4-bit A/D con...
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