Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 kΩcm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1·10 13 n/cm 2 and 5·10 13 n/cm 2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1·10 15 n/cm 2 is more than 50 µm at 100 V bias. This is sufficient to guarantee satisfactory signal/noise performance on outer layers of pixel trackers in HL-LHC experiments.
Depleted monolithic CMOS active pixel sensors (DMAPS) have been developed in order to demonstrate their suitability as pixel detectors in the outer layers of a toroidal LHC apparatus inner tracker (ATLAS ITk) pixel detector in the high-luminosity large hadron collider (HL-LHC). Two prototypes have been fabricated using 150 nm CMOS technology on high resistivity (≥ 2 kΩ·cm 2 ) wafers. The chip size is equivalent to that of the current ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and the analog readout of the DMAPS. The other is a fully monolithic DMAPS including fast readout digital logic that handles the required hit rate. In order to yield a strong homogeneous electric field within the sensor volume, thinning of the wafer was tested. The prototypes were irradiated with X-ray up to a total ionization dose (TID) of 50 Mrad and with neutrons up to non-ionizing energy loss (NIEL) of 10 15 n eq /cm 2 . The analog readout circuitry maintained its performance after TID irradiation, and the hit-efficiency at > 10 −7 noise occupancy was as high as 98.9 % after NIEL irradiation.
This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration. The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper.
The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.
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