This brief leads the synthesis of fractional-order memristor (FOM) emulator circuits. To do so, a novel fractional-order integrator (FOI) topology based on current-feedback operational amplifier and integer-order capacitors is proposed. Then, the FOI is substituting the integer-order integrator inside flux- or charge-controlled memristor emulator circuits previously reported in the literature and in both versions: floating and grounded. This demonstrates that FOM emulator circuits can also be configured at incremental or decremental mode and the main fingerprints of an integer-order memristor are also holding up for FOMs. Theoretical results are validated through HSPICE simulations and the synthesized FOM emulator circuits can easily be reproducible. Moreover, the FOM emulator circuits can be used for improving future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices, and programmable analog circuits.
A technique for reducing the offset at the frequencydependent pinched hysteresis loop of memristor emulator circuits is introduced. The technique involves at integrating two DC voltage sources in the emulator circuits, keeping not only the circuit size reasonable, but also the original behavior equation of the memristor emulator circuits is not drastically modified. Using this technique, we will show how the offset is reduced due to the nonlinearities of the integrator circuit and of the multiplying core, principally. The technique is applicable to floating and grounded memristor emulator circuits, whose design is based on analog multipliers.
This paper provides a novel configuration to design a multi-scroll chaotic oscillator employing unity-gain cells (UGCs). The inclusion of multi-breakpoints to create a high-order negative nonlinear resistor (NR) is realized by the parallel combinations of basic cells. The breakpoints are controlled with resistors and tuning with level shifters. The multiscroll chaotic attractor has been optimized with ±1.5V by using standard CMOS technology of 0.35µm AMS. Hspice simulations performed in the state plane and in the time domain are shown.
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