A technique for reducing the offset at the frequencydependent pinched hysteresis loop of memristor emulator circuits is introduced. The technique involves at integrating two DC voltage sources in the emulator circuits, keeping not only the circuit size reasonable, but also the original behavior equation of the memristor emulator circuits is not drastically modified. Using this technique, we will show how the offset is reduced due to the nonlinearities of the integrator circuit and of the multiplying core, principally. The technique is applicable to floating and grounded memristor emulator circuits, whose design is based on analog multipliers.

This paper provides a novel configuration to design a multi-scroll chaotic oscillator employing unity-gain cells (UGCs). The inclusion of multi-breakpoints to create a high-order negative nonlinear resistor (NR) is realized by the parallel combinations of basic cells. The breakpoints are controlled with resistors and tuning with level shifters. The multiscroll chaotic attractor has been optimized with ±1.5V by using standard CMOS technology of 0.35µm AMS. Hspice simulations performed in the state plane and in the time domain are shown.

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A new implementation of Chua's circuit employing unity-gain cells (UGC) as the active building blocks to emulate the behavior of the nonlinear resistor (NR) and the grounded inductor is introduced. The breakpoints and slopes associated to the NR as well as the numeric value of the inductor can be adjusted by the control resistors. The proposed circuit is suitable for implementation with the commercially available integrated circuit (IC) AD844AN from Analog Devices. Hspice simulations and experimental results are included, showing close agreement with theoretical conclusions.