Offset reduction on memristor emulator circuits

Abstract

A technique for reducing the offset at the frequencydependent pinched hysteresis loop of memristor emulator circuits is introduced. The technique involves at integrating two DC voltage sources in the emulator circuits, keeping not only the circuit size reasonable, but also the original behavior equation of the memristor emulator circuits is not drastically modified. Using this technique, we will show how the offset is reduced due to the nonlinearities of the integrator circuit and of the multiplying core, principally. The technique is applicable to floating and grounded memristor emulator circuits, whose design is based on analog multipliers.

Fractional‐Order Memristor Emulator Circuits

“…To obtain an FOM from integer-order memristor, the integrator circuit of the latter must be replaced by FOI circuit, as shown in Figure 4(a). Following the analysis given in [15,25], the behavioral model is deduced as…”

“…where and are DC voltage sources to control horizontally and vertically the offset of the dependent-frequency pinched hysteresis loop on the voltage-current plane, respectively [25], and denotes the fractional-order integral operator of (i) Riemann-Liouville and Caputo fractional integral…”

“…According to Figure 5 in [18], the emulator circuit has also an IOI circuit and if it is exchanged with Figure 1, then a fractional-order chargecontrolled grounded memristor emulator circuit is obtained, as shown in Figure 4(b). Hence, following the analysis given in [18,25], one obtains…”

A Novel Floating Memristor Emulator with Minimal Components

“…In fact, multipliers are often used to realize the product of voltage and flux (current and charge) for the design of the flux-controlled (charge-controlled) memristor emulators [21][22][23][24][25][26][27]. Different from the above design methods, however, herein the multipliers are employed to construct a floating voltage-controlled resistor (VCR).…”

“…Therefore, a replacement that behaves like a real memristor is still urgently needed to allow ordinary researchers to study memristor-based practical applications. Indeed, many memristor emulator circuits have been developed in recent years [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32]. For example, using a JFET to implement the required nonlinearity, a memristor emulator constructed with five operational amplifiers, a floating capacitor, a large number of resistors, and an analog multiplier is presented in [19].…”