It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.
This paper presents unique case studies describing the use of EBAC technique. Front as well as backside EBAC on relatively smaller nets is presented to isolate logic fails which are otherwise hard to capture using conventional failure analysis techniques.
There are several methods commonly used to locate the area of interest (AOI), such as using layout landmarks, applying laser marks, focus ion beam marks, etc. This paper discusses another method which can improve the job efficiency and cost-effectiveness by introducing the combination of laser marking and laser deprocessing technique (LDT) as a quick way to deprocess the AOI. It further explores LDT to improve the job efficiency and throughput in logic devices to achieve cost-saving targets. An experiment was performed on a 14nm technology node prototype chip that integrated logic and SRAM. The proposed LDT has demonstrated itself to be a useful method to increase the job efficiency by performing in batch and easy to locate the AOI upon loading the sample for SEM inspection. It is also a simple and cost-effective way to delayer comparing to other methodologies.
Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.
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