This paper presents unique case studies describing the use of EBAC technique. Front as well as backside EBAC on relatively smaller nets is presented to isolate logic fails which are otherwise hard to capture using conventional failure analysis techniques.
It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.
Research into modeling, verification and circuit applications of transformers in CMOS is reviewed. Transformer concepts and topologies are followed by discussions of the use of transformers for power and area reduction, bandwidth enhancement, modeling, etc. Finally, conclusions are drawn on future research directions for the use of transformers in CMOS design.
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