In this paper, the design of a low-cost ultra-high-frequency (UHF) Radio Frequency IDentification (RFID) tag chip with an advanced encryption standard (AES) cryptographic engine is presented. The design of digital baseband is verified on a Field-Programmable Gate Array (FPGA) platform. The whole chip, including a radio frequency frontend, an analog frontend, an Electrically Erasable Programmable Read-Only Memory (EEPROM), and a baseband with AES engine, is taped out on Semiconductor Manufacturing International Corporation (SMIC) 0.13mm process. The chip area is 1 Â 1 mm2, in which 0.6 Â 0.3 mm2 is covered by the digital baseband. The power consumption of the entire tag chip is 20.9 mW. The design can work on both two modes of the standard ISO 18000-6C mode and the security enhanced ISO 18000-6C mode. To the best of our knowledge, it is the first UHF passive RFID tag chip with AES algorithm in the baseband.
This paper presents a wide-band digitally controlled oscillator (OCO) applied in all digital phase locked loop (AOPLL) of which the tuning range is 3GHz-5.3GHz. Capacitor tank of the oscillator contains 3 major arrays: coarse tuning bank, medium tuning bank and fine tuning bank (including fractional tuning capacitors), which are all formed by varactors. Post-layout simulation is done to verify its performance on SMIC 40nm process. The oscillator phase noise is -137dBc/Hz at 3MHz, 3.7GHz, and power consumption is 8.6mW and 7mW respectively where center frequency is 3GHz and 5.3GHz.
An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of −12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process.
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