We fabricate and characterize asymmetric memristors which show a very strong single-sided hysteresis. When biased in one direction there is hysteresis and in the opposite direction there is a lack of hysteresis. We demonstrate that this apparent lack is actually hysteresis on a much faster time-scale. We further demonstrate that this form of asymmetric behavior correlates very well to the asymmetric structure and function of an actual synapse. The asymmetric memristor device presented here is necessary to correctly implement spike-timing-dependent-plasticity STDP in mixed memristor/neuron hybrid systems as an artificial synapse. These devices show the required characteristics for implementing the asymmetric form of long-term potentiation (LTP) and long-term depression (LTD) of a synapse between two neurons, where symmetric memristor devices do not. Signals from a presynaptic neuron are sent via its axon across the synapse to the dendrite of a postsynaptic neuron. Postsynaptic neuron signals sent to subsequent neurons have an influence on the strength of any further presynaptic neuron signals received by the postsynaptic neuron across the synapse. These signals are grouped into spike triplets within the framework of STDP and, as we experimentally show here, can be implemented with asymmetric memristors, not standard symmetric memristors.
Anisotropic etching processes for mesa structure formation using fluorinated plasma atmospheres in an electron cyclotron resonance (ECR) plasma etcher were studied on Novasic substrates with 10 µm thick 3C-SiC(100) grown on Si(100). To achieve reasonable etching rates, a special gas inlet system suitable for injecting SF6 into the high density downstream Ar ECR plasma was designed. The influence of the etching mask material on the sidewall morphology was investigated. Masking materials with small grain sizes are preferable to achieve a desired shape. The evolution of the mesa form was investigated in dependence on the gas composition, the applied bias, the pressure and the composition of the gas atmosphere. The achieved sidewall slope was 84.5 deg. The aspect ratios of the fabricated structures in the developed residue free ECR plasma etching process were between 5 and 10. Mesa structures aligned to [100] and [110] directions were fabricated.
Three-terminal junction devices were realized in graphene grown heteroepitaxially on semiinsulating silicon carbide as well as in AlGaN/GaN heterostructures grown by MOCVD on sapphire containing a two dimensional electron gas. These nanoelectronic devices were fabricated using electron beam lithography. In both types of heterostructures room temperature electrical measurements revealed a pronounced nonlinear electrical behavior of the fabricated nanoelectronic devices. The obtained voltage rectification at room temperature demonstrates the feasibility of func-tional three-terminal junctions in heterostructures consisting of types of high carrier mobility struc-tures than classical III-V semiconductor heterostructures.
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