Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SOC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering the 5T Portless SRAM, an original multiplexor structure is presented that offers a significant gain in active energy consumption. The multiplexor benefits from a hard line duplication technique that copies an addressed line into an other line in one clock cycle. The advantages of the latter duplication technique are presented in details. Moreover Portless bitcell is more stable, suffers less leakage than 6T SRAM bitcell. The paper confirms that Portless SRAM is a candidate alternative structure to 6T SRAM in advanced technologies.
International audienceSRAM 6T bitcell suffers many limitations in advanced technology nodes among which varaibility issues. Various alternatives have been experimented and the paper focuses the 5T portless bitcell. Read and write operations are operated by varying voltage conditions. The results in have been reviewed in CMOS 32nm and improvements have been provided. The bitcells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bitcell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption. The paper details the portless operation and current-mode reading based an simulation results. A matrix testchip is currently under fabrication in bulk CMOS 32nm
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