SRAM portless bitcell and current-mode reading

Abstract

International audienceSRAM 6T bitcell suffers many limitations in advanced technology nodes among which varaibility issues. Various alternatives have been experimented and the paper focuses the 5T portless bitcell. Read and write operations are operated by varying voltage conditions. The results in have been reviewed in CMOS 32nm and improvements have been provided. The bitcells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bitcell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption. The paper details the portless operation and current-mode reading based an simulation results. A matrix testchip is currently under fabrication in bulk CMOS 32nm