Abstract:Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SOC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering the 5T Portless SRAM, an original multiplexor structure is presented that offers a significant gain in active ener… Show more
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