This paper presents the design methodology, simulation and measurement results of a CMOS 12GHz Rotary Travelling Wave Voltage Controlled Oscillator. The different simulations (electrical using SPICE and electromagnetical using HFSS) are presented. These results are compared to a theoretical approach and measurements. The oscillator has been fabricated in a 0.13µm RF-CMOS technology. The phase noise at a 1MHz offset from the carrier is105dBc/Hz and the tuning range is 1.2GHz for a global consumption of 25mA.
A fully integrated 2 A fractional Synthesizer (included VCO, Loop Filter, Xtal oscillator negative impedance) is implemented in a 0.4 um, 45 GHz (SiGe) BiCMOS. The measured close in phase noise is -106 dBdHz at 900 MHz using 26 MHz comparison frequency and frequency resolution less than 5Hz is achieved. The VCO's inductors are not integrated in order to test the PLL performance on different frequency's range. Using a 200 KHz close loop bandwidth the level of the tones generated, when critical channels are synthesized, exceed the GSM transmitter specifications without applying any dithering technique. The very low close in phase noise and low level of tone generation, make it suitable for "indirect GMSK VCO modulation" application
This paper reports a 12 GHz rotary travelling wave (RTW) voltage controlled oscillator designed in a 130 nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. The RTW VCO exhibits a −106 dBc/Hz at 1 MHz and a 30 mW power consumption with a sensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are presented.
3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and other design techniques have been used. The maximum composite spurious (due to PLLs coupling, Xtal spurious and fractional spurs) is -35dBc (in +/-15MHz range). Each PLL has a frequency range from 2.2GHz to 4.4GHz with a worst-case (over process and temperature) integrated rms of 1.2deg at 3.8GHz. The frequency step (31.25KHz) is obtained with a 10bit SD clocked at 32MHz. The single PLL draw 35 mA from 3.8 Volt supply (regulated internally to 2.8 or 3.4 Volt) for 3.2 mm 2 .
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.