Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction

Abstract

3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has been implemented while to avoid static coupling a large use of differential structure and other design techniques have been used. The maximum composite spurious (due to PLLs coupling, Xtal spurious and fractional spurs) is -35dBc (in +/-15MHz range). Each PLL has a frequency range from 2.2GHz to 4.4GHz with a worst-case (over process and temperature) integrated rms of 1.2deg at 3.8GHz. The frequency step (31.25KHz) is obtained with a 10bit SD clocked at 32MHz. The single PLL draw 35 mA from 3.8 Volt supply (regulated internally to 2.8 or 3.4 Volt) for 3.2 mm 2 .