Comparison between RTW VCO and LC QVCO 12 GHz PLLs

Benabdeljelil, F.; Jacquemod, G.; Tatinian, William; Lucchi, P.; Borgarino, M.; Carpineto, L.

doi:10.1007/s10470-012-9885-9

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…To perform a quadratic demodulation, it is necessary to have at least two 90 • -phase shifted signals. A VCO enables this operation to be carried out [12]. LC tanks are the most popular circuits to realize a VCO.…”

Section: Ro Designmentioning

confidence: 99%

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2.

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Section: Ro Designmentioning

confidence: 99%

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

View full text Add to dashboard Cite

show abstract

“…These results show that our structure is more or less at the state of the art with a better phase noise and a simpler design, so with a very low-silicon area. Other comparisons between LC tank and RTW VCOs or LC tank and Ring VCOs can be found, respectively, in [28,29]. Moreover, another LC tank design in 22 nm technology is depicted in [30].…”

Section: Comparison With Classical Lc Tank Vcomentioning

confidence: 99%

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor.

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“…The integration of this RO in a VCRO will make this measurement possible and will decrease the PN. Table 1 gives a comparison of this circuit with two other QVCO topologies (LC tank and RTW) [10]. The figure of Merit is given by the following equation:…”

Section: Ro Layout and Measurementsmentioning

confidence: 99%

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Wei

Jacquemod

Leduc

et al. 2019

Active and Passive Electronic Components

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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Comparison between RTW VCO and LC QVCO 12 GHz PLLs

Cited by 7 publications

References 10 publications

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

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