An effective resistive-switching effect has been observed in silicon nitride (Si 3 N 4 ) dielectrics in Ag/Si 3 N 4 /Al memory cells. The ratio of the low resistance to high resistance state was larger than 10 7 at ±1.2 V for a 10 nm thick Si 3 N 4 layer. This switching behavior is attributed to a change in the conductivity of the Si 3 N 4 dielectrics, depending on whether nitride-related traps are filled with electrons under positive biases or unfilled under negative biases. This assertion is experimentally confirmed from the relationship between the amount of charges trapped in the Si 3 N 4 layer and the corresponding changes in its resistance with respect to bias voltages. In addition, the formation or dissolution of the conductive path is confirmed by conductive atomic force microscopy current images.
We measured the linewidth enhancement factor (alpha factor) of InAs quantum dot (QD) laser diodes (LDs) with two different QD structures. One is a normal QD LD with the same energy bandgap for each active QD layer, while the other is chirped with different energy bandgaps. The differential gain of the chirped InAs QD LDs is found to be about five times smaller than that of normal InAs QD LDs, whereas no overall wavelength shift with injection currents is observed in both QD LDs. The alpha factor is approximately five times higher in the chirped InAs QD LDs than in the normal InAs QD LDs. This relatively large alpha factor in the chirped InAs QD LDs is attributed to the asymmetrical, wide inhomogeneous gain profile.
We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 • C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 • C. In addition, the highest traps density of 6.84 × 10 18 cm −3 was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.
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