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This paper presents a novel technique to enhance Antenna-onChip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

A 60 GHz miniaturised, low loss on-chip bandpass filter (BPF) based on open-loop resonators is presented. Overlapping of the BPF's resonators leads to miniaturisation and introduces a mixed coupling configuration. Moreover, its resonators are folded to minimise the size and the insertion loss (IL). H-shaped defected ground structures are also used to reduce IL and to improve the out of band rejection. The measured IL, return loss, centre frequency, and bandwidth are 2.85 dB, 18 dB, 59 GHz and 15.5 GHz with a chip size of 368 × 262 µm 2 including pads.

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This letter presents a high efficiency, and small group delay variations 12-24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18 µm CMOS technology and tested. A measured power gain (|S 21 |) of 10.5 ² 0.7 dB and a measured small group delay variation of ²20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50 mW.

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