Sorting is a core operation in many applications. In particular large problem sorting has received increased attention due to many big data problems that require sorting. Most large problem sorters use variants of merge sorting. Traditional merge sorters are implemented of trees having a linear cost in resources with respect to the number of sequences merged. In this paper, we present an FPGA implementation that scales logarithmic and allows therefore merging several thousand sorted sequences in one run through the chip. For achieving high throughput, we use speculative execution techniques, pipelining of critical paths, simplified inter-level tree communications and parameterizing stage sizes for allowing trade-offs between utilization/throughput and stalling rates. Our implementation can merge sort up to 4096 sequences of 64-bit keys at 253MHz (16K sequences at 188MHz). In contrast with previous works, we research and present an implementation that sorts end-to-end on real hardware showing that the resource utilization of the needed buffering infrastructure is much higher than the sorter itself. A case study utilizing a Xilinx VC709 board merges 1024 sequences of the Graysort benchmark from and to DRAM at 80% peak DDR-3 memory throughput.
Memory throughput is one of the major bottlenecks for accelerator performance. Now that Zynq UltraScale+ systems are being deployed at exascale to edge, it is important to understand its limitations and optimizations possible for developers. In this paper, we extensively evaluate the memory performance and behaviour for various AXI ports combinations, burst sizes, access patterns, and the number of accelerators per AXI port. Our results on ZCU102 and Ultra 96 boards show that 1) effective throughput of these systems is only 75% and 92.5% of theoretical maximum respectively, 2) 128 and 192 byte burst size is often optimal, 3) AXI ports of the same type may not always exhibit similar behaviour, 4) multiplexing accelerators in PL can provide better throughput distribution compared to multiplexing in PS, and 5) using all AXI ports does not lead to the highest performance.
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