Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems

Manev, Kristiyan; Vaishnav, Anuj; Koch, Dirk

doi:10.1109/icfpt47387.2019.00029

Cited by 26 publications

(15 citation statements)

References 7 publications

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“…V. RELATED WORK Manev et al [4] have characterized DRAM access from the PL side on the ZU9EG. The highest throughput from DRAM they could achieve was 75 % of the theoretical maximum using three out of four AXI ports, avoiding the usage of ports 1 and 2 simultaneously.…”

Section: Characterization Outcomementioning

confidence: 99%

Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs

Mattheeuws

Forsberg

Kurth

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Reconfigurable heterogeneous systems-on-chips (SoCs) integrating multiple accelerators are cost-effective and feature the processing power required for complex embedded applications. However, to enable their usage in real-time settings, it is crucial to control interference on the shared main memory for reliable performance. Interference causes performance degradation due to simultaneous memory requests by components such as CPUs, caches, accelerators, and DMAs.We propose a methodology to characterize the interference to multicore host processors caused by accelerators implemented in the FPGA fabric of reconfigurable heterogeneous SoCs. Based on it, we extend the roofline model to account for performance degradation of the computing platform. The extended model allows to determine in an efficient way at which point memory interference becomes critical for a given platform and workload.We apply our methodology to a modern Xilinx UltraScale+ SoC integrating a multicore ARM Cortex-A CPU and a Kintex-grade FPGA. To the best of our knowledge, our results experimentally show for the first time that programs with intensities below 5 flop/byte -workloads with low cache locality -can suffer from slowdowns of up to an order of magnitude.

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Section: Characterization Outcomementioning

confidence: 99%

Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs

Mattheeuws

Forsberg

Kurth

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…While embedded platforms provide limited bandwidth [58]- [60], e.g. less than 4.5 GB/s for Ultra96 and ZC706, sustaining peak bandwidth even on larger devices, such as ZCU104, is nontrivial [59]. This is aggravated as multiple applications are collocated on a single device [60]- [62]; and ii) underutilised PEs due to the mismatch of diverse layer shapes [15]- [19].…”

Section: Challenges Of Fpga-based Cnn Inference Enginesmentioning

confidence: 99%

unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation

Venieris¹,

Fernández-Marqués²,

Lane³

2021

Preprint

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Single computation engines have become a popular design choice for FPGA-based convolutional neural networks (CNNs) enabling the deployment of diverse models without fabric reconfiguration. This flexibility, however, often comes with significantly reduced performance on memory-bound layers and resource underutilisation due to suboptimal mapping of certain layers on the engine's fixed configuration. In this work, we investigate the implications in terms of CNN engine design for a class of models that introduce a pre-convolution stage to decompress the weights at run time. We refer to these approaches as on-the-fly. To minimise the negative impact of limited bandwidth on memorybound layers, we present a novel hardware component that enables the on-chip on-the-fly generation of weights. We further introduce an input selective processing element (PE) design that balances the load between PEs on suboptimally mapped layers. Finally, we present unzipFPGA, a framework to train on-thefly models and traverse the design space to select the highest performing CNN engine configuration. Quantitative evaluation shows that unzipFPGA yields an average speedup of 2.14× and 71% over optimised status-quo and pruned CNN engines under constrained bandwidth and up to 3.69× higher performance density over the state-of-the-art FPGA-based CNN accelerators.

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“…The first selected configuration was a sorter with k = 128, w = 4, 128-bit datapath and an operating frequency of 250MHz. This frequency can saturate the achievable bandwidth of that port at 128 bits per cycle [28] and was achieved with the throughput optimisation (internally with w = 8). As shown in figure 8, the sorter achieves a speedup of up to around 36 times for data that fit in a single pass (k 2 = 16384) and above around 15 times for all other input sizes.…”

Section: B Use Case 1: Sortingmentioning

confidence: 99%

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

Papaphilippou

Brooks

Luk

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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This work improves on the latest research about sorting acceleration on FPGAs. An efficient design is introduced for sorting data that fit on-chip, with the additional functionality to merge sorted sublists recursively, for an input of arbitrary length. While many-leaf mergers are conventionally single-rate, a novel technique in our approach is to use a parallel merge tree only for the latest stages of the merge tree, to enable bandwidth-adapted multi-rate many-leaf merge. Our open-source RTL generator produces sorting peripherals with customisable parallelism and data format. We evaluate our FPGA design as an 128-bit wide peripheral on an MPSoC platform, with a speedup of up to 49 times over the A53 core for sorting, and up to 27 times speedup for our specialized database analytics application.

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Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems

Cited by 26 publications

References 7 publications

Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs

Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs

unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

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