Large Utility Sorting on FPGAs

Database sizes are growing faster than the processing power in the post-Moore era due to the advent of big data applications, which make hardware acceleration mandatory. We propose dynamic stream processing using partial reconfiguration to provide a high-performance solution to runtime-known problems. This work researches the benefits of applying resource elastic techniques when building the execution pipeline.

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“…Factors can also be dependant on the particular operation performed. For does not exclusively depend on the merging throughput [7].…”

Section: Discussionmentioning

confidence: 99%

Resource Elastic Database Acceleration

Manev

Koch

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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“…The merge tree sorting algorithm is favored for FPGA-based sorters due to its massive data parallelism, less control overhead and regular memory access patterns [1], [2], [3], [4], [5], [6], [7], [8], [9]. In this section, we first introduce the HBM-based FPGAs.…”

Section: Background Reviewmentioning

confidence: 99%

“…Using a combination of various hardware merge units with different rates, we can build a complete binary tree that consumes l unsorted input sequences concurrently at its leaves and outputs p sorted elements at its root every cycle [4], [6], [7], [8]. Figure 4 shows the architecture of a merge tree [7].…”

Section: Dram-based Merge Tree Sorting Acceleratormentioning

confidence: 99%

“…Sorting is one of the fundamental computation kernels in many big data applications and there have been continuous efforts on designing high-performance sorting accelerators on FPGAs [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. Most of these sorting accelerators are based on the multi-way merge tree sort algorithm [1], [2], [3], [4], [5], [6], [7], [8], [9], due to its massive data parallelism and regular memory access patterns. Before the maturing of the high-bandwidth memory (HBM) technology, these sorters were usually implemented on DRAM-based FPGAs and bounded by the off-chip memory bandwidth [7], [8].…”

Section: Introductionmentioning

confidence: 99%

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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Qiao¹,

Guo²,

Fang³

et al. 2022

Preprint

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The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth, as the required on-chip resource usage grows at a much faster rate and would bound the sorting performance in turn. Second, designers need an in-depth understanding of HBM's characteristics to effectively utilize the HBM bandwidth. To tackle these challenges, we present TopSort, a novel two-phase sorting solution optimized for HBM-based FPGAs. In the first phase, 16 merge trees work in parallel to fully utilize 32 HBM channels' bandwidth. In the second phase, TopSort reuses the logic from phase one to form a wider merge tree to merge the partially sorted results from phase one. TopSort also adopts HBM-specific optimizations to reduce resource overhead and improve bandwidth utilization. TopSort can sort up to 4 GB data using all 32 HBM channels, with an overall sorting performance of 15.6 GB/s. TopSort is 6.7× and 2.2× faster than state-of-the-art CPU and FPGA sorters.

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“…There are many ways this work can be expanded. The unused FPGA resources could be spent on high-throughput [4], [5] or large scale sorters [18] for implementing a full H/W sort-merge join. Different stream processors could be attached for accelerating more complex analytics, such as for filtering and machine learning.…”

Section: Future Work and Conclusionmentioning

confidence: 99%

Accelerating the Merge Phase of Sort-Merge Join

Papaphilippou

Pirk

Luk

2019

2019 29th International Conference on Field Programmable Logic and Applications (FPL)

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We present an efficient, high-throughput and scalable hardware design for accelerating the merge phase of the sort-merge join operation. Sort-merge join is one of the fundamental join algorithms and among the most frequently executed operations in relational databases. It has been the focus of various recent pieces of research, each having different shortcomings and usually only focusing on the sort phase. In this paper, a new parallel sort-merge join architecture is developed, that provides data streaming functionality and high throughput. The key idea of the paper is the use of a novel design for a co-grouping engine, with which the input data are summarised on-the-fly. In this way, the operation is performed on streams of data, preserving the linear access pattern for faster data movement and also eliminates the need for a replay buffer/cache. In contrast to related work, our approach does not make assumptions about the value distribution of the input data and applies to any input size and width. We evaluate the design on a Zynq UltraScale+ based platform, and show that there is up to 3.1 times speedup over the host processor, even without accelerating the sort phase, while still taking into account the data transfers from and to main memory in Linux.

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Large Utility Sorting on FPGAs

Cited by 14 publications

References 8 publications

Resource Elastic Database Acceleration

Resource Elastic Database Acceleration

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Accelerating the Merge Phase of Sort-Merge Join

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