A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally shared. The existence of a unique poweroptimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed prior to spacing optimization. By using this order of wires, optimality of the combined solution is guaranteed (as compared with any other ordering and spacing of the wires). Timing-aware power optimization is enabled by simultaneously considering timing criticality weights and activity factors for the signals. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from high-end microprocessor circuits in 65 nm technology. Interconnect power reduction of 17% on average has been observed in such bundles.

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The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimally-tuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sum-of-delays problem. An iterative algorithm to find the optimally-tuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed.

We have developed the deposition technology of WSi thin films 4 to 9 nm thick with high temperature values of superconducting transition (T c~4 K). Based on deposed films there were produced nanostructures with indicative planar sizes ~100 nm, and the research revealed that even on nanoscale the films possess of high critical temperature values of the superconducting transition (T c~3 .3-3.7 К) which certifies high quality and homogeneity of the films created. The first experiments on creating superconducting single-photon detectors showed that the detectors' SDE (system detection efficiency) with increasing bias current (I b ) reaches a constant value of ~30% (for =1.55 micron) defined by infrared radiation absorption by the superconducting structure. To enhance radiation absorption by the superconductor there were created detectors with cavity structures which demonstrated a practically constant value of quantum efficiency >65% for bias currents I b 0.6I c . The minimal dark counts level (DC) made 1 s -1 limited with background noise. Hence WSi is the most promising material for creating single-photon detectors with record SDE/DC ratio and noise equivalent power (NEP).

The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its line-to-line weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout cross-capacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial high-end microprocessor and yielded 17% power reduction and 9% delay reduction in top-level interconnects is presented. ACM Reference Format:Moiseev, K., Wimer S., and Kolodny A. 2009. Power-Delay optimization in VLSI microprocessors by wire spacing.