Power-delay optimization in VLSI microprocessors by wire spacing

Abstract

The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its line-to-line weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout cross-capacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial high-end microprocessor and yielded 17% power reduction and 9% delay reduction in top-level interconnects is presented. ACM Reference Format:Moiseev, K., Wimer S., and Kolodny A. 2009. Power-Delay optimization in VLSI microprocessors by wire spacing.

The complexity of VLSI power-delay optimization by interconnect resizing

“…Delay and power models in (2.3) and (2.4) are commonly used in the literature [6], and the parameters in their expressions are not subject to optimization. The total sum of delays, maximal delay and total interconnect power consumption are given respectively by:…”

“…Shifting wires in one layer doesn't affect the spacing and width of the orthogonal wires in the layers above it and below it. The length changes of wires in layers above and below of optimized layer is negligible for all practical cases [6]. Until recently the sizes of interconnects were allowed to change continuously and the implied power-delay optimal tradeoff could be formulated as a convex programming problem, for which classical search algorithms are applicable [7].…”

Interconnect power and delay optimization by dynamic programming in gridded design rules

“…We showed how a DP algorithm finds the power-delay Pareto curve [24] representing optimal design. Some papers proposed to minimize a weighted sum of the power and delay [9] or minimize a product of their powers [23]. It is a straightforward consequence that any two-variable function that is monotonic increasing in any of its variables will achieve its minimum at a point of the powerdelay shape-function.…”

“…Simultaneous wire sizing and spacing is effective because wire-towire capacitances, which are the dominant part of interconnect capacitance [11], are very sensitive to inter-wire spacing. Several interconnect resizing algorithms were proposed to increase clock frequency [3] [4] [5] [6], to reduce dynamic power [7] [8], and to maintain some tradeoff between both [9]. Most of the techniques assume that interconnect width and space can vary in a continuous range allowed by design rules.…”

“…A general approach for the solution of such problems by using efficient data structures has been reported in [20]. Simultaneous optimization of all nets in order to achieve minimum delay or power has been addressed by several authors [5] [7] [9]. Such optimizations account for the block's area constraint and obtain the provable minimum which stems from the convexity of the power and delay expressions.…”