We present nanometer-scale physical structures and analysis algorithms for characterizing tip width and shape for critical dimension atomic force microscopy (CD-AFM). Automated CD-AFM measurements will be used in the future, and a robust methodology is demonstrated for ensuring long-term repeatability of width measurements on sub-100 nm structures. Structures are designed and chosen for their width uniformity on the sub-nm scale, as well as for their well defined shapes that can be deconvolved from the scan data to yield a precise image of the tip. We address the contributions of tool precision and linearity, tip shape and line-edge roughness of the calibration artifact to overall measurement stability.
The decrease in critical dimension (CD) of integrated circuits (IC) always challenges metrology tools capabilities. In less than ten years we will reach the limit of CMOS technology with typical printed gate length less than 20 nm and physical gate length of less than 15nm. Advanced R&D departments must already address today all the issues related to so small devices otherwise the roadmap requirements would not be fulfilled. Indeed most of the issues are directly related to metrology capabilities such as precise control of the shape of etched features, sidewall roughness, wafer CD uniformity, and mask inspection (…). All these parameters will represent a bottleneck for advanced patterning if metrology tools are unable to measure them with a precision better than few nanometers. In this paper we show that 3D metrology is mandatory to succeed in reaching future roadmap requirements. We address in details the CD AFM technique capabilities which is a potential candidate for advanced patterning metrology. The experimental data are compared with today's reference: cross-sectional analysis (X-SEM). We also discuss on other techniques such as scatterometry and top view CD-SEM which are also candidates for 3D metrology.
We present 3-dimensional atomic force profiler (AFP) measurements on die-scale flatness (20 mm x 20 mm) after copper and STI CMP. True metrology is achieved for patterned wafers. Wafers are vacuummounted on a flat chuck, as they would be in a stepper, so wafer warpage and strain-related non-planarity are not present. The results of this new technique are compared against current measurement techniques. For logic, memory and System-on-a-chip, we discuss the implications of wafer planarity going into subsequent photolithography steps.
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