For increasing the bit-density in the conventional binary logic system, various efforts have been made toward implementing single devices with two threshold voltage (VTH) via the negative differential resistance (NDR) phenomenon.

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Multi‐valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming “big data” era. The feasibility of MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS2–graphene–WSe2 van der Waals heterostructure is evolved to a double‐NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double‐NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature‐dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double‐peak NDT device and a p‐channel transistor through Cadence circuit simulation is theoretically demonstrated.

Multi‐valued logic (MVL) technology that utilizes more than two logic states has recently been reconsidered because of the demand for greater power saving in current binary logic systems. Extensive efforts have been invested in developing MVL devices with multiple threshold voltages by adopting negative differential transconductance and resistance. In this study, a reconfigurable, multiple negative‐differential‐resistance (m‐NDR) device with an electric‐field‐induced tunability of multiple threshold voltages is reported, which comprises a BP/ReS2 heterojunction and a ReS2/h‐BN/metal capacitor. Tunability for the m‐NDR phenomenon is achieved via the resistance modulation of the ReS2 layer by electrical pulses applied to the capacitor region. Reconfigurability is verified in terms of the function of an MVL circuit composed of a reconfigurable m‐NDR device and a load transistor, wherein staggered‐type and broken‐type double peak‐NDR device operations are adopted for ternary inverter and latch circuits, respectively.

Figure 8. Single-electron transistors (SETs). a) Schematic structure and b) transfer I-V characteristic of a typical SET. c) Schematic diagram and scanning electron microscopy image of the two-gate SET. d) Transfer I-V characteristic of the two-gate SET at V in2 = 0 V and 0.2 V. c,d) Reproduced with permission. [18] Copyright 2000, IEEE. e) Circuit diagram of the universal literal gate and its periodic V in −V out characteristic. Reproduced with permission. [98] Copyright 2003, IEEE. f) Schematic of the two-input hybrid MOSFET-SET device. g) The output voltage as a function of two input gate voltages. f,g) Adapted with permission. [103] Copyright 2009, IEEE. h,i) Schematic diagram of the Si EQD SET (h) and its typical two-peak transfer characteristic (i). j) Contour plot demonstrating I D as a function of V DS and V G enabling ternary and quaternary operation regimes. h-j) Reproduced with permission. [105]

Negative Differential Resistance In article number 2202799, a reconfigurable, multiple negative differential resistance (m‐NDR) device, which features electric‐field‐induced tunability of multiple threshold voltages, is presented by Jin‐Hong Park and co‐workers. Its reconfigurability is verified in terms of the function of a multi‐valued logic circuit composed of a reconfigurable m‐NDR device and a load transistor; staggered‐type and broken‐type double peak‐NDR device operations are adopted for ternary inverter and latch circuits, respectively.

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