Looking Beyond 0 and 1: Principles and Technology of Multi‐Valued Logic Devices

Abstract

Figure 8. Single-electron transistors (SETs). a) Schematic structure and b) transfer I-V characteristic of a typical SET. c) Schematic diagram and scanning electron microscopy image of the two-gate SET. d) Transfer I-V characteristic of the two-gate SET at V in2 = 0 V and 0.2 V. c,d) Reproduced with permission. [18] Copyright 2000, IEEE. e) Circuit diagram of the universal literal gate and its periodic V in −V out characteristic. Reproduced with permission. [98] Copyright 2003, IEEE. f) Schematic of the two-input hybrid MOSFET-SET device. g) The output voltage as a function of two input gate voltages. f,g) Adapted with permission. [103] Copyright 2009, IEEE. h,i) Schematic diagram of the Si EQD SET (h) and its typical two-peak transfer characteristic (i). j) Contour plot demonstrating I D as a function of V DS and V G enabling ternary and quaternary operation regimes. h-j) Reproduced with permission. [105]

Defect-Engineered Semiconducting van der Waals Thin Film at Metal–Semiconductor Interface of Field-Effect Transistors

“…In particular, we observed an intermediate state (10–15 V) under a backward gate voltage sweep in which the current level is nearly independent of V G , which originated from partial suppression of hole transport caused by the valence band potential barrier at the s-CNT/H-MoS 2 interface (Figure S9). The corresponding transfer characteristic with a stable intermediate state (i.e., g m (transconductance) ≈ 0) can be utilized for ternary MVT, which can operate as multistate logic gates when paired with V G -independent resistive-load transistor. , The MVT behavior is characterized by two distinct threshold voltages ( V TH ) that were clearly defined by two peaks in the inverse subthreshold swing (1/SS)– V G plot, distinguishing our MOSSFET from general binary devices (Figure S10). To elucidate the dominant charge transport mechanism at different V G and V D , we constructed the Fowler-Nordheim (F-N) plot (ln (I/ V 2 ) vs 1/ V ) from the output curves measured at different V G (Figure S11).…”

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits

“…In the NDT region, the differential transconductance, defined as g m = d I DS /d V GS , has a negative value that is not present in common n- or p-type field-effect transistors. This NDT region plays an essential role in representing the intermediate state of the ternary inverter . One of the advantages obtained by adopting a heterojunction TR with NDT characteristics while implementing a ternary inverter is that the TR of a conventional binary CMOS inverter can be easily replaced .…”

“…To solve this problem, many technologies such as neuromorphic systems, − system on chip (SOC), and in-memory computing have been developed for efficient data processing and reduced power consumption. Among these technologies, multivalued logic (MVL) technology , has been explored as a potential alternative to conventional binary logic systems due to its ability to represent more than two logic states and its compatibility and substitutability with conventional CMOS systems. , By enabling the representation of multiple data, MVL technology promotes rapid data processing and low power consumption by reducing the number of interconnect lines that increase parasitic capacitances and resistances. , Also, the reduction of interconnect lines increases the integration density by minimizing the chip area. For example, by employing a ternary, quaternary, or quinary system instead of the conventional binary system, the complexity of the overall system is expected to decrease by 64%, 50%, or 44%, respectively .…”

Performance Enhancement of Organic Ternary Logic Circuits through UV Irradiation and Geometry Optimization

“…The rapid progress of artificial intelligence and the widespread adoption of internet of things technology have created a demand for efficient computing systems capable of processing large data sets with low power consumption and high speed. [1][2][3] Conventional Boolean computing systems encounter challenges in managing such substantial data demands. Multivalued logic (MVL) circuits, which can handle more than two logic states, have emerged as a promising solution.…”

“…Multivalued logic (MVL) circuits, which can handle more than two logic states, have emerged as a promising solution. [3][4][5][6][7][8] MVL enables the design of integrated circuits with high information density, thus reducing interconnects and achieving power efficiency and high speed.…”