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This paper presents the design of a low-voltage and low-power frontend. It consists of a low noise amplifier (LNA) which integrates with mixer, and downconverts an 24-GHz RF input signal to an IF of 8-GHz. The first stage (LNA) uses complementary-push-pull configuration to save power consumption as well as to increase the trans-conductance and gain. A PMOS transistor is biased in the moderate inversion region functions as active load for LNA. It also converts the input voltage signal to current signal for the succeeding block which is a down-conversion mixer. The single-balanced mixer is accomplished to convert high frequency to intermediate frequency. The designed RF front-end uses the folded architecture to reduce the supply voltage and hence, power consumption. The whole circuit draws only 1.53 mA from 0.9-V power supply. The proposed circuit showed conversion gain of 12 dB and noise figure of 5.5 dB for-12dBm LO power.

Abstract. In this paper, we present a new low-power Programmable Gain Amplifier (PGA) with a DC-offset cancellation to reduce chip area, cost and power. The PGA adjusts 8-level gains from 4dB to 60dB using the 8 CMOS switches and 16 passive resistors in parallel, and DC-offset circuit is based on a Miller effect technique. It is fabricated using Magnachip/SK Hynix 0.18-μm CMOS 1poly-6metal process. The proposed system showed excellent gain error of less than 0.24dB, very small die area of 0.015mm 2 and low power consumption of 1.137mW.