This paper presents a high gain and low power 24-GHz power amplifier (PA) for the short range automotive radar. The proposed circuit is implemented using TSMC 0.13-µm RF CMOS (f T /f max =120/140 GHz) technology, and it is powered by a 1.5-V supply. To improve power gain of the amplifier, it has a 2-stage cascode scheme. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF (radio frequency) are used to reduce parasitic capacitances at the band of 24 GHz. The proposed RF amplifier has low cost and low power dissipation since it is realized using all CMOS processes. The proposed circuit showed the smallest chip size of 0.12 mm 2 , the lowest power dissipation of 44.3 mW and the highest power gain of 24.04 dB as compared to recently reported research results.
Abstract-Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS g m -boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.Index Terms-CMOS, RF frontend, IF direct conversion receiver (IF-DCR), low noise amplifier (LNA), downconversion mixer
Abstract. In this paper, we present a new low-power Programmable Gain Amplifier (PGA) with a DC-offset cancellation to reduce chip area, cost and power. The PGA adjusts 8-level gains from 4dB to 60dB using the 8 CMOS switches and 16 passive resistors in parallel, and DC-offset circuit is based on a Miller effect technique. It is fabricated using Magnachip/SK Hynix 0.18-μm CMOS 1poly-6metal process. The proposed system showed excellent gain error of less than 0.24dB, very small die area of 0.015mm 2 and low power consumption of 1.137mW.
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