A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

Rastegar, Habib; Ryu, Jee-Youl

doi:10.1016/j.mejo.2015.05.006

Cited by 30 publications

(5 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The MMIC Matrix Distributed Low Noise Amplifier presents a high gain and low noise compared to the work of [14,15]. The linearity of this amplifier is very high compared to [14][15][16] and reaches up to 20 dBm.…”

Section: Resultsmentioning

confidence: 99%

UWB-MMIC Matrix Distributed Low Noise Amplifier

Bakkali

Elkhaldi

Hamzi

et al. 2020

The 14th International Conference on Interdisciplinarity in Engineering—INTER-Eng 2020

View full text Add to dashboard Cite

In this paper, a 3.1–11 GHz ultra-wideband low noise amplifier with low noise figure, high power gain S21, low reverse gain S12, and high linearity using the OMMIC ED02AH process, which employs a 0.18 μm Pseudomorphic High Electron Mobility Transistor is presented. This Low Noise Amplifier (LNA) was designed with the Advanced Design System simulator in distributed matrix architecture. For the low noise amplifier, four stages were used obtaining a good input/output matching. An average power gain S21 of 11.6 dB with a gain ripple of ±0.6 dB and excellent noise figure of 3.55 to 4.25 dB is obtained in required band with a power dissipation of 48 mW under a supply voltage of 2 V. The input compression point 1 dB and third-order input intercept point are −1.5 and 23 dBm respectively. The core layout size is 1.8 × 1.2 mm2.

show abstract

Section: Resultsmentioning

confidence: 99%

UWB-MMIC Matrix Distributed Low Noise Amplifier

Bakkali

Elkhaldi

Hamzi

et al. 2020

The 14th International Conference on Interdisciplinarity in Engineering—INTER-Eng 2020

View full text Add to dashboard Cite

show abstract

“…Achieving high efficiency UWB LNA means to satisfy a hard trade-off related to the LNA characteristics over the wide band of UWB spectrum, namely, in/out impedance matching, high and flat gain, low dissipated power, low noise figure (NF), and finally compact chip size. Various LNA topologies have been proposed to address such issues [4][5][6][7][8][9][10][11][12][13][14][15]. Among them the distributed amplifier configuration has been largely investigated [4][5][6], based on cascading multistage it enables to widen the bandwidth and increase the gain.…”

Section: Introductionmentioning

confidence: 99%

“…The common gate topology is another solution involved to UWB LNAs design [7][8][9][10], thanks to its absolutely real input impedance, the input/output matching network is guaranteed over a wide frequency range; nevertheless, its low power gain and poor noise performance weaken its operation. Another configuration able to cover large bandwidth matching network is the utilisation of common source transistor with input inductor and capacitor (LC) bandpass filter (BPF) [11][12][13][14][15], however, the use of inductors increases both the silicon area and the NF.…”

Section: Introductionmentioning

confidence: 99%

Efficient UWB low noise amplifier with high out of band interference cancellation

Taibi

Trabelsi

Slimane³

et al. 2017

IET Microwaves, Antennas & Propagation

View full text Add to dashboard Cite

This work provides a new co‐design methodology of ultrawide band (UWB) low‐noise amplifier (LNA) with high out of band interference cancellation. The solution consists to cascade a selective microstrip UWB bandpass filter (BPF) with the proposed 0.18 µm complementary metal–oxide–semiconductor‐based LNA. Indeed, the usefulness of this co‐design technique is to address the interference mitigation through the BPF and amplification function by using the LNA. The proposed solution remains powerful since the out of band interferences are well avoided with an efficient amplification performance while well fulfilling UWB requirements, i.e. good matching over a wide bandwidth from 3.2 to 10.64 GHz, 17 dB of power gain (S21), the noise figure varies between 2.5 and 5.7 dB, and the dissipated power (PDC) is typically 16.5 mW. It is relevant to point out that the computed figure‐of‐merit of the proposed circuit is 29.03 which is very competitive compared with state‐of‐the art.

show abstract

“…Direct conversion receiver (DCR) is the best candidate among the various receiver architectures due to the low cost and low power issues. However, large dc offset, LO leakage, 1/f noise, and I/Q mismatch are the bottlenecks of DCR receiver [1,2].…”

Section: Introductionmentioning

confidence: 99%

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Rastegar¹,

Ryu²

2016

JSTS:Journal of Semiconductor Technology and Science

Self Cite

View full text Add to dashboard Cite

Abstract-Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS g m -boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.Index Terms-CMOS, RF frontend, IF direct conversion receiver (IF-DCR), low noise amplifier (LNA), downconversion mixer

show abstract

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

Cited by 30 publications

References 15 publications

UWB-MMIC Matrix Distributed Low Noise Amplifier

UWB-MMIC Matrix Distributed Low Noise Amplifier

Efficient UWB low noise amplifier with high out of band interference cancellation

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Contact Info

Product

Resources

About