Bias temperature-dependent characteristics of nanoscale silicon-oxide-nitride-oxide-silicon memories are investigated under program/erase (P/E) Fowler–Nordheim (FN) stresses. In the erased cell, FN stress time evolution is found to be a similar physical process to the recovery of interface traps (NIT) that takes place under the dynamic negative bias temperature instability stress. In addition, anode hole injection induced holes are trapped in the bottom oxide, both in the erase and in the read conditions of the erased cell, and make significant roles in the reverse hysteresis and higher power-law exponent n at higher temperature in P/E cycled erased cells. While the temperature-independent n=0.3 is observed in the programed cell, the temperature-sensitive n=0.36–0.66 is observed in the erased cell.
In this letter, a Ka-band cavity resonator using micromachining process is presented. A two-port cavity resonator is designed using the three-dimensional (3-D) design software, HP HFSS. The cavity resonator is fabricated on a Si substrate and bonded with a Quartz wafer. The resonator shows the resonant frequency of 39 GHz, the insertion loss of 4.6 dB, and the loaded quality factor (Q L ) and unloaded quality factor (Q U ) of 44.3 and 107, respectively.
PurposeThe purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded.Design/methodology/approachEmbedded technology has been implemented on a multilayer PCB to enhance the performance and functionality and to decrease the power noise. Decoupling capacitors were directly positioned on the inner power planes of a board, which resulted in low‐loop inductance through the minimized length of the interconnection from the chips to the PCB's power delivery network.FindingsA low‐noise PCB was successfully designed and fabricated using an embedding process for the discrete decoupling capacitors. It was demonstrated that such an approach offers lower interconnection inductance and quiet noise performance, including highly efficient propagation noise suppression at wideband frequencies.Research limitations/implicationsMost conventional simulation techniques offer expectations for the signal characteristics on the time domain to minimize bit error rates in application systems. Further development work will focus on the integrated simulation models including the equivalent circuits for the transmission line and power noise effects to improve the accuracy of the signal performance.Originality/valueThis paper presents a new approach for improving generating and propagating noise performance through the use of an embedded decoupling capacitor design methodology.
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