We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.
A push-pull silicon photonic Mach-Zehnder modulator (MZM) driver is presented which uses a switched capacitor approach to generate a ∼2 V peak-to-peak differential 4-level pulse amplitude modulation (PAM-4) signal. The driver chip includes a Gray encoder and retiming flip-flops. The switched capacitor approach allows driving the lumped silicon photonic MZM with reduced power consumption compared with the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400 Gbit/s 802.3 Ethernet. The chip was fabricated using a 65 nm CMOS technology and flipchipped on top of the silicon photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4 dB extinction ratio for a 36 Gbit/s (18 Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of 0.11 mm 2 and consumes 236 mW from 1.2 to 2.4 V supply voltages. This corresponds to an energy efficiency of 6.55 pJ/bit including Gray encoder and retiming, or 5.37 pJ/bit for the driver circuit only.
We 1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The worst-case (across process, temperature and supply voltage corners) aperture time of the sampling front end is 17ps for a differential input voltage swing of 200mV, sufficient to resolve a 56Gb/s (28Gbaud) PAM-4 signal. The power consumption is 55mW from 1.0V and 1.2V supply voltages.
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