A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

Abbaszadeh, Asgar; Azerbaijan, Anasystem; Sadeghipour, Khosrov Dabbagh

doi:10.1109/icdsp.2011.6004958

Cited by 11 publications

(5 citation statements)

References 7 publications

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“…Moreover, the proposed 10 taps RNS-MAC filter structure attains a reduction in the area of about 84.11% over the scheme suggested (Park et al , 2004). Furthermore, area minimization of about 71.67% was achieved in the proposed architecture when examined with the reconfigurable FIR filter suggested by Abbaszadeh et al (2011). From this observation, it is inferred that the suggested RNS MAC realization uses a minimum amount of logic elements over the existing realizations.…”

Section: Resultsmentioning

confidence: 75%

“…The latest advancement in FPGA technologies encompasses several competent digital signal processor (DSP) cores to accommodate various complicated algorithmic approaches. However, it is essential to amend the optimal algorithm to have efficient system hardware usage (Xilinx Incorporation, 2022; Abbaszadeh et al , 2011; Pari and Vaithiyanathan, 2017; James et al , 2020). Speed enhancement, as well as parallel processing in digital filters, is obtained by incorporating the idea of RNS.…”

Section: Literature Surveymentioning

confidence: 99%

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A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

Mariammal²,

Vaithiyanathan³

2022

WJE

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Purpose Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers. Design/methodology/approach RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity. Findings In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure. Originality/value The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

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Section: Resultsmentioning

confidence: 75%

Section: Literature Surveymentioning

confidence: 99%

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

Mariammal²,

Vaithiyanathan³

2022

WJE

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“…Synopsys Design Compiler is used to analyze area, delay, and power for 32/28 nm standard cell. The work [9] proposes a latest hardware productive reconfigurable FIR filter design based on the binary signed subcoefficient approach. The requirements of hardware for multiplexer units is drastically decreased when compared to traditional techniques using proposed coefficient representation method.…”

Section: A Harware Efficiencymentioning

confidence: 99%

Enhancing Techniques for Adaptable Decision Feedback Balancer for 5G Communication

2024

IJRASET

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This complete review examines two basic parts of cutting edge correspondence frameworks. First and foremost, it investigates novel plan procedures and models for Adaptable Decision Feedback Balancer (ADFB) in rapid correspondence frameworks. Strategies like look-into tables, disseminated math, and prescient equal branch slicers are utilized to upgrade union rates, throughput, and mistake execution while limiting equipment intricacy. The proposed plans exhibit significant advancement in region, power proficiency, and rationale usage across different regulation plans, channel models, and portability situations. Furthermore, the examination digs into Super Dependable Low Idleness Correspondence (SDLIC) headways inside the 5G New Radio (NR) downlink, tending to actual layer difficulties determined in 3GPP Delivery 15. The review presents a clever correspondence framework utilizing super codes to moderate between image impedance in remote conditions. Also, inventive equal plans for high velocity Choice Input Adjusters (CIAs) and equipment proficient models for versatile balancers utilizing disseminated number-crunching are introduced. The joined discoveries contribute significant bits of knowledge into streamlining versatile balancers for group of people yet to come correspondence frameworks and progressing SDLIC in 5G NR.

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“…The SNR can be re-written as (7). To reduce the hardware complexity of the scaling operation, α is selected in α = 2 β manner, where β is shown as (8). As a result, the scaling operation can be implemented with shift registers.…”

Section: Adaptive Scaling Algorithmmentioning

confidence: 99%

“…Different from the conventional 2's complement system (TCS), the input signal and coefficients are represented with stochastic bit streams in SC-based FIR filters. As a result, the complex arithmetic operations in TCS circuits can be mapped into quite simple logic gates operation [2,[6][7][8][9][10][11]. Reference [6] proposes a bipolar mapping scheme and presents a complete stochastic FIR filter architecture, where the XNOR gate can implement the multiplication.…”

Section: Introductionmentioning

confidence: 99%

A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

et al. 2021

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Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

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A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

Cited by 11 publications

References 7 publications

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

Enhancing Techniques for Adaptable Decision Feedback Balancer for 5G Communication

A High-Accuracy Stochastic FIR Filter with Adaptive Scaling Algorithm and Antithetic Variables Method

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