Driver circuit for a PAM‐4 optical transmitter using 65 nm CMOS and silicon photonic technologies

Abstract

A push-pull silicon photonic Mach-Zehnder modulator (MZM) driver is presented which uses a switched capacitor approach to generate a ∼2 V peak-to-peak differential 4-level pulse amplitude modulation (PAM-4) signal. The driver chip includes a Gray encoder and retiming flip-flops. The switched capacitor approach allows driving the lumped silicon photonic MZM with reduced power consumption compared with the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400 Gbit/s 802.3 Ethernet. The chip was fabricated using a 65 nm CMOS technology and flipchipped on top of the silicon photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4 dB extinction ratio for a 36 Gbit/s (18 Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of 0.11 mm 2 and consumes 236 mW from 1.2 to 2.4 V supply voltages. This corresponds to an energy efficiency of 6.55 pJ/bit including Gray encoder and retiming, or 5.37 pJ/bit for the driver circuit only.

A DC-coupled 50 Gb/s 0.064 pJ/bit thin-oxide level shifter in 28 nm FDSOI CMOS

“…Table I shows a comparison of this work with other reported CMOS level shifters for cascoded output inverter applications. The table combines AC and DC-coupled level shifters and shows that this work is competitive while [6] 65 nm 25 Gb/s no [7] 65 nm 18 Gb/s yes [10] 45 nm SOI 14 Gb/s no [11] 130 nm 1 Gb/s yes This work 28 nm SOI 50 Gb/s yes…”

“…To generate a driving voltage that is larger than 1 V with inverter based driver circuits, a cascoded inverter driver (Fig. 1) [2,6,7] or a pseudo differential output driver [8,9] can be used.…”

“…To obtain the required bandwidth an AC coupled level shifter [2,6,10] is frequently implemented, but can introduce bit errors when sending bit streams with a long sequence section of consecutive identical bits if not sized properly or working at a lower rate than designed for. DC-coupled level shifters [7,11] do not have this problem and hence work for multi-rate applications, but are typically limited in maximum speed. This work presents a high speed DC-coupled thin-oxide transistorsonly level shifter in a 28 nm fully depleted silicon on insulator (FDSOI) technology that enables data rates up to 50 Gb/s.…”

Silicon photonic modulators for PAM transmissions

“…Advanced submicron CMOS processes have voltage outputs less than 2 V, which is low compared to the V π of optical modulators in a generic silicon photonic process. Innovative designs (e.g., [90]) in both Table 3.…”

Design and Performance Evaluation of Multi-Gb/s Silicon Photonics Transmitters for High Energy Physics

“…(b) CMOS gate-like topology. Different transistor stacking arrangements can be exploited with the aid of floating supply rails[26,31,[33][34][35]. Dealing with ring modulators (RMs), cathode and anode driver stages are sometimes separated (dashed line) to provide a slight forward bias to the pn-junction[32].…”