Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Sadeghipour, Khosrov Dabbagh; Townsend, Paul D.; Ossieur, Peter

doi:10.1109/iscas.2015.7168956

Cited by 6 publications

(6 citation statements)

References 8 publications

(15 reference statements)

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“…Similar to the phase difference, the output of the slicer φ u comprises a random noise component φ u,n and a bias φ u,B . The instantaneous difference φ q between the output of the Alexander phase detector φ u and the output of the pseudolinearized model (K n φ e,n + K B φ e,B ) can be approximated as random distributed quantization noise 2 . This noise term is added to obtain a more accurate model [32], [33].…”

Section: Pseudo-linearized Phase Detector Gain Using One Thresholdmentioning

confidence: 99%

“…T O support ever increasing data rates, the traditional onoff-keying (OOK) non-return-to-zero (NRZ) signaling scheme employed in wireline and optical interconnects is progressively being replaced by 4-level pulse amplitude modulation (PAM-4) [1], [2]. Thanks to the higher spectral efficiency, the data rate can be doubled within the same bandwidth budget.…”

Section: Introductionmentioning

confidence: 99%

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The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs

Verbeke

Torfs

Rombouts

2021

IEEE Trans. Circuits Syst. I

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Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented.

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Section: Pseudo-linearized Phase Detector Gain Using One Thresholdmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs

Verbeke

Torfs

Rombouts

2021

IEEE Trans. Circuits Syst. I

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“…As an alternative, solutions tailored to the particular modulation format have gained momentum. Custom receiver circuits have been shown for both duobinary signals [27] as well as for 4-PAM modulation [28]. These designs show that high-symbol rate operation combined with multilevel modulation require advanced circuitry; the latter is realized in recent CMOS and BiCMOS technologies and with broadband circuit impedance matching leading to more complex designs and smaller tolerances than in the case of traditional NRZ modulation.…”

Section: B Transceiver Complexitymentioning

confidence: 99%

“…In the absence of residual ISI, FR gives rise to P E = 2 L−1 L Q 1 σν . Using a similar reasoning as for PR signaling, upper and lower bounds on P E are easily derived when isi max < 1, by bounding the individual terms in (28)(29).…”

Section: Error Performance Analysismentioning

confidence: 99%

Performance analysis of pre-equalized multilevel partial response modulation for high-speed electrical interconnects

Guenach

Jacobs

Kozicki

et al. 2017

Computers & Electrical Engineering

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In this paper, we first review the baseband modulation techniques intended for use in short-reach, high-speed electrical interconnects. Then we briefly introduce the high-level design concepts of the investigated electrical interconnect, indicating the main limitations and outlining the transceiver complexity related to the advanced modulation designs. We further investigate finite-complexity linear pre-equalization under an average transmit power constraint of both full-response and precoded partial response signaling with pulse amplitude modulation (L-PAM) mapping. For a representative electrical interconnect, we argue that the constellation size, the type of modulation, the detection method as well as the number of pre-equalizer taps should be carefully selected in order to achieve target error performance at data rates between 100 Gbit/s and 200 Gbit/s. We show that for many combinations of above mentioned parameters, precoded duobinary 4-PAM yields the best error performance for a fixed average transmit power.

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“…T HE continuous demand for higher data rates pushes broadband wireline and optical communication systems toward the extensive use of multi-lane transceiver architectures [1], [2]. In such applications, the clock and data recovery (CDR) block requires multi-phase clocks with phase adjusting capability which if implemented digitally, can be realized by using digital to phase converters (DPCs [3]).…”

Section: Introductionmentioning

confidence: 99%

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

Khanghah¹,

Sadeghipour²,

Kelly³

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Index Terms-Digital to phase converter (DPC), clock and data recovery (CDR), phase interpolator (PI), wireline and optical communication.

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Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Cited by 6 publications

References 8 publications

The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs

The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs

Performance analysis of pre-equalized multilevel partial response modulation for high-speed electrical interconnects

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

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