Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules.Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.
We present a 65nm embedded DRAM cell (0.127 µm 2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL) (1). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided substrate guardrings with fully landed tungsten contacts. The bitline structure and the deep trench capacitor are designed for high transfer ratio and low RC constant which ensure high performance and sufficient sensing signal. The pass transistor is strain engineered to boost on current and employs optimized S/D junctions to help attain sub-pA off current. This technology has produced fully-functional 2Mb prototype embedded macros with sub-1.5ns latency and sub-2ns random cycle times for on-processor caches. The low leakage device developed also enables for the first time a low standby power SOI technology.
For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications.
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