Selenium was used in the first solid state solar cell in 1883 and gave early insights into the photoelectric effect that inspired Einstein’s Nobel Prize work; however, the latest efficiency milestone of 5.0% was more than 30 years ago. The recent surge of interest towards high-band gap absorbers for tandem applications led us to reconsider this attractive 1.95 eV material. Here, we show completely redesigned selenium devices with improved back and front interfaces optimized through combinatorial studies and demonstrate record open-circuit voltage (V
OC) of 970 mV and efficiency of 6.5% under 1 Sun. In addition, Se devices are air-stable, non-toxic, and extremely simple to fabricate. The absorber layer is only 100 nm thick, and can be processed at 200 ˚C, allowing temperature compatibility with most bottom substrates or sub-cells. We analyze device limitations and find significant potential for further improvement making selenium an attractive high-band-gap absorber for multi-junction device applications.
Large-grain absorber formation through selenization techniques is a promising route for high performance chalcogenide solar cells. Understanding and subsequently controlling such grain growth is essential in improving absorber quality and developing absorbers with unique optoelectronic and morphological properties. We explain the essential role of liquid selenium in the grain growth of Cu 2 ZnSnSe 4 (CZTSe) absorbers from Cu 2 ZnSnS 4 nanoparticles by proposing a liquid-assisted grain growth mechanism. Through the use of a multizone rapid-thermalprocessing furnace, control of liquid Se delivery to the film and the Se (g) atmosphere during processing is shown to result in novel absorbers with tunable properties. Additionally, the processing parameters necessary for high quality CZTSe absorbers, the role of nanoparticle properties, and the role of alkali metal dopants in the liquid-assisted growth mechanism are shown. Ultimately, record nanoparticle-based device performance of 9.3% is achieved for selenized CZTSe absorbers.
We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript
Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference-it contains multiple arrays of phase change memory (PCM)devices, each array capable of storing 512 × 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weighterror. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ∼0.6%)
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