Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format

Abstract

Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference-it contains multiple arrays of phase change memory (PCM)devices, each array capable of storing 512 × 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weighterror. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ∼0.6%)

AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator

“…This work focuses on NVM CiM arrays using phase-change memory (PCM) cells, specifically following a recent prototype in silicon by Khaddam-Aljameh et al (2021).…”

“…Non-volatile memory (NVM) approaches are particularly relevant to TinyML applications, where we need single-chip solutions with all memory on-chip, and with low leakage. A recent phase change memory (PCM) based CiM chip (Khaddam-Aljameh et al, 2021) demonstrated 10 TOPS/W at full utilization.…”

“…To date, research on CiM focuses on high throughput, fully-parallel hardware, with performance evaluated on either peak numbers (assuming 100% utilization) (Khaddam-Aljameh et al, 2021), or on large benchmark models such as ResNet-50 (Shafiee et al, 2016;Ankit et al, 2019;Jia et al, 2021), which also achieve high utilization. In contrast, this paper describes end-to-end model-hardware co-design of TinyML DNNs with an always-on PCM CiM accelerator.…”

“…SRAM CiM has the significant advantage of availability in cutting-edge CMOS technologies, but is limited to storing two-levels per bitcell. A strong alternative is non-volative memory (NVM) (Shafiee et al, 2016;Ankit et al, 2019), such as flash (Merrikh-Bayat et al, 2017) or memristive devices, such as metal-oxide resistive RAM (ReRAM) (Hu et al, 2018;Yao et al, 2020), and phase-change memory (PCM) (Boybat et al, 2018;Ambrogio et al, 2018;Narayanan et al, 2021). Most NVM devices can store multiple levels per cell.…”

“…For instance, PCM devices that can compute with an equivalent 8-bit precision (Giannopoulos et al, 2018) have been demonstrated. In this paper we employ PCM-based CiM, modeled after Khaddam-Aljameh et al (2021).…”