HERMES-Core—A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh, Riduan; Stanisavljević, Miloš; Mas, Jordi Fornt; Karunaratne, Geethan; Brändli, Matthias; Liu, Feng; Singh, Abhairaj; Müller, Silvia M.; Egger, Urs; Πετρόπουλος, Αναστάσιος; Antonakopoulos, Theodore; Brew, Kevin; Choi, S.; Ok, I.; Lie, Fee Li; Saulnier, Nicole; Chan, V.; Ahsan, Ishtiaq; Narayanan, V.; Nandakumar, S. R.; Gallo, Manuel Le; Francese, Pier Andrea; Sebastian, Abu; Eleftheriou, Evangelos

doi:10.1109/jssc.2022.3140414

Cited by 63 publications

(50 citation statements)

References 46 publications

(41 reference statements)

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“…Recently, Khaddam‐Aljameh et al [100,101] reported about a 256 × 256 in‐memory core based on the 14 nm technology with multilevel PCM. They combined 256 linearized analog‐digital converters based on current controlled oscillators with a local digital processing unit and showed reliable matrix‐vector multiplication over 1 GHz, as well as a high classification accuracy when this in‐memory computation core was applied for deep learning.…”

Section: Pcm For Non‐von Neumann Computersmentioning

confidence: 99%

“…I G U R E 7 (a) Resistance distribution of four states in phase-change memory (PCM) cells; (b) the corresponding ramp-down current pulses.From Xie et al[81], originally published under a CC-BY license.signals at the same time, which necessitates complex algorithms with high memory requirements, making it one of the areas where inmemory computing is expected to reduce memory and computing resources. They showed similar accuracy of the chosen compressed sensing algorithm on their prototype multilevel PCM chip consisting of more than 256 k PCM devices, as compared with fixed-point implementation with matrix and vector elements quantized to 4 bit.Recently, Khaddam-Aljameh et al[100,101] reported about a 256 × 256 in-memory core based on the 14 nm technology with multilevel PCM. They combined 256 linearized analog-digital converters based on current controlled oscillators with a local digital processing unit and showed reliable matrix-vector multiplication over 1 GHz, as well as a high classification accuracy when this in-memory computation core was applied for deep learning.The temperature dependence of such in-memory computing devices based on PCMs was discussed by Boybat et al [102] They investigated the conductance states for multilevel PCMs in which synaptic weights for deep learning applications were stored by characterization of a large number of 10,000 doped Ge 2 Sb 2 Te 5based PCMs and modeled the temperature dependence of the conductance states.…”

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confidence: 99%

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Recent developments in phase‐change memory

Ehrmann

Błachowicz

Ehrmann³

et al. 2022

Applied Research

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Phase-change memory (PCM) belongs to the nonvolatile solid-state memory techniques. Usually, a chalcogenide is sandwiched between two conductive electrodes and data are stored by setting each cell to a low-resistance (crystalline) or a high-resistance (amorphous) state. Switching between these states is relatively fast, which makes phase-change random access memories (PCRAMs) highly interesting for nonvolatile memories. Multilevel cells, which can store more than 1 bit per cell, and multilayer high-density memory arrays have also been reported as advantages of PCRAM. Writing currents and data retention, on the other hand, still show potential for optimization. This review gives an overview of the most recent developments in new material compositions and material-related optimization of PCM in comparison with already produced PCM.

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Section: Pcm For Non‐von Neumann Computersmentioning

confidence: 99%

mentioning

confidence: 99%

Recent developments in phase‐change memory

Ehrmann

Błachowicz

Ehrmann³

et al. 2022

Applied Research

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“…Resistance-based IMC cores, and more specifically those based on phase-change memory (PCM) devices, have recently shown promising results [43]. In a resistance-based IMC core, we can encode certain values as conductances of PCM devices placed in a mesh-like array.…”

Section: B In-memory Computingmentioning

confidence: 99%

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Guirado¹,

Rahimi²,

Karunaratne³

et al. 2022

Preprint

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Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) systems have been recently proved to be one of the most energy-efficient options, due to hypervector manipulations in the memory itself that reduces data movement. Although implementations of HDC on single IMC cores have been made, their parallelization is still unresolved due to the communication challenges that these novel architectures impose and that traditional Networks-on-Chip and Networks-in-Package were not designed for. To cope with this difficulty, we propose the use of wireless on-chip communication technology in unique ways. We are particularly interested in physically distributing a large number of IMC cores performing similarity search across a chip, and maintaining the classification accuracy when each of which is queried with a slightly different version of a bundled hypervector. To achieve it, we introduce a novel over-the-air computing that consists of defining different binary decision regions in the receivers so as to compute the logical majority operation (i.e., bundling, or superposition) required in HDC. It introduces moderate overheads of a single antenna and receiver per IMC core. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. It is demonstrated that the proposed approach allows to both bundle at least three hypervectors and scale similarity search to 64 IMC cores seamlessly, while incurring an average bit error ratio of 0.01 without any impact in the accuracy of a generic HDC-based classifier working with 512-bit vectors.

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“…In this context, filamentary memristors and phase change memories can be used in a very elegant and energy-efficient way. These devices can act as analog synaptic weights enabling neural network multiply-and-accumulate operations directly in memory by relying on Ohm's law and Kirchoff's current law [1][2][3][4][5][6][7] . Low-power systems of this kind could provide essential services: for example, medical devices could analyze patient measurements and detect life-threatening emergencies or automatically adjust treatment.…”

Section: Introductionmentioning

confidence: 99%

Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks

Bonnet

Hirtzlin

Majumdar

et al. 2023

Preprint

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Safety-critical sensory processing applications, like medical diagnosis, require making accurate decisions based on a small amount of noisy input data. For these applications, using Bayesian neural networks, able to quantify the uncertainty of the predictions, is a superior approach to using conventional artificial neural networks. However, because of the probabilistic nature of Bayesian neural networks, they can be computationally intensive to use for inference stage and thus not well suited for extreme-edge applications. An emerging idea to solve this problem is to use the intrinsic probabilistic nature of memristors to efficiently implement Bayesian neural network inference: the variability in the resistance of memristors would represent the probability distribution of weights in Bayesian neural networks. However, when using memristors, statistical effects follow the laws of device physics, whereas in Bayesian neural networks, those effects can take on arbitrary shapes. In this work, we overcome this difficulty by adopting a dedicated synapse architecture based on two memristors, and by training Bayesian neural networks with a dedicated variational inference technique that includes a “technological loss” to take into account specificities of memristor physics. This technique allowed us to program a two-layer Bayesian neural network on 75 physical crossbar arrays of 1,024 memristors, incorporating CMOS periphery circuitry to do in-memory computing, to classify arrhythmia in electrocardiograms. Our experimental neural network classified heartbeats with high accuracy, and estimated the certainty of its predictions. In the case of uncertain predictions, it differentiated between ambivalent heartbeats (aleatoric uncertainty), and heartbeats with never-seen patterns (epistemic uncertainty). We show that our technique can also be used with phase change memories, by employing a different “technological loss” term. The great advantage of this approach is its low energy consumption: we estimate an 800 times improvement in energy efficiency compared to a GPU performing the same task.

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Cited by 63 publications

References 46 publications

Recent developments in phase‐change memory

Recent developments in phase‐change memory

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks

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HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Cited by 63 publications

References 46 publications

Recent developments in phase‐change memory

Recent developments in phase‐change memory

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks

Contact Info

Product

Resources

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs