The scanning capacitance microscope ͑SCM͒ is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope ͑SPM͒. As reported in Edwards et al. ͓Appl. Phys. Lett. 72, 698 ͑1998͔͒, scanning capacitance spectroscopy ͑SCS͒ is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.
Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.
Modern day VLSI Semiconductor devices are manufactured using a chemical mechanical polish (CMP) process. The resultant layers are planar with respect to one another and should be easy to remove. All that needs to be done is to lap the layer until the region of interest is exposed. In practice this has been difficult. This article describes the combination of processes that are required to take full advantage of the strength of deprocessing techniques (lapping, plasma and gel controlled wet chemical deprocessing) to deliver a perfectly planar sample for inspection. A discussion on the thought process required to adequately select the proper chemicals for the gel controlled etch is given. Finally, a typical deprocessing flow is described. It is concluded that this combined solution enables planarity to be maintained across 100% of the device surface. There is less chance the failure site is damaged by the deprocessing.
With the recent advances in instrumentation, automation and spectrometer design, the Electron Beam Tester is fast becoming a standard tool for design verification and failure analysis of Very Large Scale Integrated Circuit (VLSI) technology products. This paper presents a brief overview of the principles of operation and a discussion of the different testing modes.The application of voltage contrast to VLSI technology is illustrated with a few typical examples taken from failure analysis and design verification stages of memory and microprocessor products.Present limitations and future trends of Electron Beam Testing are discussed.
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