Ambient and solution-processable, low-leakage, high capacitance gate dielectrics are of great interest for advances in low-cost, flexible, thin-film transistor circuitry. Here we report a new hafnium oxide-organic self-assembled nanodielectric (Hf-SAND) material consisting of regular, alternating π-electron layers of 4-[[4-[bis(2-hydroxyethyl)amino]phenyl]diazenyl]-1-[4-(diethoxyphosphoryl) benzyl]pyridinium bromide) (PAE) and HfO2 nanolayers. These Hf-SAND multilayers are grown from solution in ambient with processing temperatures ≤150 °C and are characterized by AFM, XPS, X-ray reflectivity (2.3 nm repeat spacing), X-ray fluorescence, cross-sectional TEM, and capacitance measurements. The latter yield the largest capacitance to date (1.1 μF/cm(2)) for a solid-state solution-processed hybrid inorganic-organic gate dielectric, with effective oxide thickness values as low as 3.1 nm and have gate leakage <10(-7) A/cm(2) at ±2 MV/cm using photolithographically patterned contacts (0.04 mm(2)). The sizable Hf-SAND capacitances are attributed to relatively large PAE coverages on the HfO2 layers, confirmed by X-ray reflectivity and X-ray fluorescence. Random network semiconductor-enriched single-walled carbon nanotube transistors were used to test Hf-SAND utility in electronics and afforded record on-state transconductances (5.5 mS) at large on:off current ratios (I(ON):I(OFF)) of ~10(5) with steep 150 mV/dec subthreshold swings and intrinsic field-effect mobilities up to 137 cm(2)/(V s). Large-area devices (>0.2 mm(2)) on Hf-SAND (6.5 nm thick) achieve mA on currents at ultralow gate voltages (<1 V) with low gate leakage (<2 nA), highlighting the defect-free and conformal nature of this nanodielectric. High-temperature annealing in ambient (400 °C) has limited impact on Hf-SAND leakage densities (<10(-6) A/cm(2) at ±2 V) and enhances Hf-SAND multilayer capacitance densities to nearly 1 μF/cm(2), demonstrating excellent compatibility with device postprocessing methodologies. These results represent a significant advance in hybrid organic-inorganic dielectric materials and suggest synthetic routes to even higher capacitance materials useful for unconventional electronics.

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Recent advances in semiconductor performance made possible by organic π-electron molecules, carbon-based nanomaterials, and metal oxides have been a central scientific and technological research focus over the past decade in the quest for flexible and transparent electronic products. However, advances in semiconductor materials require corresponding advances in compatible gate dielectric materials, which must exhibit excellent electrical properties such as large capacitance, high breakdown strength, low leakage current density, and mechanical flexibility on arbitrary substrates. Historically, conventional silicon dioxide (SiO2) has dominated electronics as the preferred gate dielectric material in complementary metal oxide semiconductor (CMOS) integrated transistor circuitry. However, it does not satisfy many of the performance requirements for the aforementioned semiconductors due to its relatively low dielectric constant and intransigent processability. High-k inorganics such as hafnium dioxide (HfO2) or zirconium dioxide (ZrO2) offer some increases in performance, but scientists have great difficulty depositing these materials as smooth films at temperatures compatible with flexible plastic substrates. While various organic polymers are accessible via chemical synthesis and readily form films from solution, they typically exhibit low capacitances, and the corresponding transistors operate at unacceptably high voltages. More recently, researchers have combined the favorable properties of high-k metal oxides and π-electron organics to form processable, structurally well-defined, and robust self-assembled multilayer nanodielectrics, which enable high-performance transistors with a wide variety of unconventional semiconductors. In this Account, we review recent advances in organic-inorganic hybrid gate dielectrics, fabricated by multilayer self-assembly, and their remarkable synergy with unconventional semiconductors. We first discuss the principals and functional importance of gate dielectric materials in thin-film transistor (TFT) operation. Next, we describe the design, fabrication, properties, and applications of solution-deposited multilayer organic-inorganic hybrid gate dielectrics, using self-assembly techniques, which provide bonding between the organic and inorganic layers. Finally, we discuss approaches for preparing analogous hybrid multilayers by vapor-phase growth and discuss the properties of these materials.

Solution-processed amorphous oxide semiconductors (AOSs) are emerging as important electronic materials for displays and transparent electronics. We report here on the fabrication, microstructure, and performance characteristics of inkjet-printed, low-temperature combustion-processed, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) grown on solution-processed hafnia self-assembled nanodielectrics (Hf-SANDs). TFT performance for devices processed below 300 °C includes >4× enhancement in electron mobility (μFE) on Hf-SAND versus SiO2 or ALD-HfO2 gate dielectrics, while other metrics such as subthreshold swing (SS), current on:off ratio (ION:IOFF), threshold voltage (Vth), and gate leakage current (Ig) are unchanged or enhanced. Thus, low voltage IGZO/SAND TFT operation (<2 V) is possible with ION:IOFF = 10(7), SS = 125 mV/dec, near-zero Vth, and large electron mobility, μFE(avg) = 20.6 ± 4.3 cm(2) V(-1) s(-1), μFE(max) = 50 cm(2) V(-1) s(-1). Furthermore, X-ray diffraction analysis indicates that the 300 °C IGZO combustion processing leaves the underlying Hf-SAND microstructure and capacitance intact. This work establishes the compatibility and advantages of all-solution, low-temperature fabrication of inkjet-printed, combustion-derived high-mobility IGZO TFTs integrated with self-assembled hybrid organic-inorganic nanodielectrics.

Solution processing of amorphous metal oxide materials to fabricate thin-film transistors (TFTs) has received great recent interest. We demonstrate here an optimized "ink" and printing process for inkjet patterning of amorphous indium gallium zinc oxide (a-IGZO) TFTs and investigate the effects of device structure on derived electron mobility. Bottom-gate top-contact (BGTC) TFTs are fabricated and shown to exhibit electron mobilities comparable to a-Si:H. Furthermore, a record electron mobility of 2.5 cm(2) V(-1) s(-1) is demonstrated for bottom-gate bottom-contact (BGBC) TFTs. The mechanism underlying such impressive performance is investigated using transmission line techniques, and it is shown that the semiconductor-source/drain electrode interface contact resistance is nearly an order of magnitude lower for BGBC transistors versus BGTC devices.