This letter presents a design of low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) for Bluetooth applications. By using three-level operation, the number of capacitor can be reduced. Thanks to differential operation of the designed DAC, it is no need to implement common mode reference voltage generator circuit. Moreover, in this design, optimally designed common mode capacitor is used to suppress common mode voltage drift. The fabricated chip achieves the best figure-of-merit among published DACs for Bluetooth applications.
This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 µm CMOS process. Power dissipation of this chip is 350 µW including the output buffers. The die area is 0.081mm 2 .
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