A small die area and high linearity 10-bit capacitive three-level DAC

Oshiro, Keigo; Kanemoto, Daisuke; Kanaya, Haruichi; Pokharel, Ramesh K.; Yoshida, Keiji

doi:10.1109/apccas.2012.6418997

Cited by 3 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The INL is 0.61 LSB. INL is much more improved than the previous our work (2) . The power consumption of the TLDAC is 350 µW (including output buffers) at 50 MHz Bluetooth sampling frequency.…”

Section: Measurement Resultsmentioning

confidence: 64%

See 1 more Smart Citation

A 10-bit 50MS/s 350<i>µ</i>W Small Die Area Capacitive Digital-to-Analog Converter for Bluetooth Applications

Kanemoto¹,

Oshiro

Yoshida

et al. 2014

IEEJ Trans.EIS

Self Cite

View full text Add to dashboard Cite

This letter presents a design of low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) for Bluetooth applications. By using three-level operation, the number of capacitor can be reduced. Thanks to differential operation of the designed DAC, it is no need to implement common mode reference voltage generator circuit. Moreover, in this design, optimally designed common mode capacitor is used to suppress common mode voltage drift. The fabricated chip achieves the best figure-of-merit among published DACs for Bluetooth applications.

show abstract

Section: Measurement Resultsmentioning

confidence: 64%

“…The chip was implemented on a 0.18 µm CMOS process. In this design, to improve linearity higher than the previous work (2) , randomization of capacitor array layout is also chosen. The total active area is 0.081 mm 2 .…”

Section: Design and Implementationmentioning

confidence: 99%

A 10-bit 50MS/s 350<i>µ</i>W Small Die Area Capacitive Digital-to-Analog Converter for Bluetooth Applications

Kanemoto¹,

Oshiro

Yoshida

et al. 2014

IEEJ Trans.EIS

Self Cite

View full text Add to dashboard Cite

show abstract

“…C M1 to C M5 make up the main sub-DAC and C L1 to C L5 make up the low sub-DAC. The DAC array can theoretically be realized by both binary-weighted (BW) and unitary-weighted (UW) styles [41]. The ratio between the adjacent C i in BW DAC is two, whereas that in UW DAC is one.…”

Section: B Cbw Dacmentioning

confidence: 99%

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Wang

Dehollain

2015

IEEE Sensors J.

View full text Add to dashboard Cite

This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18-µm CMOS technology and occupies an area of 1.2 mm 2 . The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 µW.Index Terms-Capacitive sensor interface, C2V, SAR ADC, CDS, opamp, noise optimization, power-efficient system.

show abstract

Design and Implementation of a Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement

Wang

Dehollain

2015

IEEE Trans. Instrum. Meas.

View full text Add to dashboard Cite

A small die area and high linearity 10-bit capacitive three-level DAC

Cited by 3 publications

References 11 publications

A 10-bit 50MS/s 350<i>µ</i>W Small Die Area Capacitive Digital-to-Analog Converter for Bluetooth Applications

A 10-bit 50MS/s 350<i>µ</i>W Small Die Area Capacitive Digital-to-Analog Converter for Bluetooth Applications

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Design and Implementation of a Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement

Contact Info

Product

Resources

About